S29CD-J_12 SPANSION [SPANSION], S29CD-J_12 Datasheet
S29CD-J_12
Related parts for S29CD-J_12
S29CD-J_12 Summary of contents
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... Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Publication Number S29CD-J_CL-J_00 ™ Notice On Data Sheet Designations Revision B Amendment 7 S29CD-J and S29CL-J Flash Family Cover Sheet for definitions. Issue Date October 11, 2012 ...
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... Questions regarding these document designations may be directed to your local sales office range. Changes may also include those needed to clarify a IO S29CD-J and S29CL-J Flash Family S29CD-J_CL-J_00_B7 October 11, 2012 ...
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... Data Sheet General Description The Spansion S29CD-J and S29CL-J devices are Floating Gate products fabricated in 110-nm process technology. These burst-mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks, using separate data and address pins. These products can operate MHz (32 Mb MHz (16 Mb), and use a single V 3.0V to 3.6V (S29CL-J) that make them ideal for today’ ...
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... Secured Silicon Sector Entry and Exit Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11. Electronic Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12. Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.2 Automatic Sleep Mode 12.3 Hardware RESET# Input Operation 12.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control S29CD-J and S29CL-J Flash Family S29CD-J_CL-J_00_B7 October 11, 2012 ...
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... Alternate CE# Controlled Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 18.8 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 18.9 PQFP and Fortified BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 19. Appendix 19.1 Common Flash Memory Interface (CFI 20. Appendix 20.1 Command Definitions 21. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 October 11, 2012 S29CD-J_CL-J_00_B7 Power-up S29CD-J and S29CL-J Flash Family 5 ...
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... Figure 18.13 DQ2 vs. DQ6 for Erase/Erase Suspend Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Figure 18.14 Synchronous Data Polling Timing/Toggle Bit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Figure 18.15 Sector Protect/Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Figure 18.16 Alternate CE# Controlled Write Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 CC1 Power-up Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 IO S29CD-J and S29CL-J Flash Family S29CD-J_CL-J_00_B7 October 11, 2012 ...
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... Tables Table 7.1 S29CD016J/CL016J (Top Boot) Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . .20 Table 7.2 S29CD016J/CL016J (Bottom Boot) Sector and Memory Address Map . . . . . . . . . . . . . . . . .21 Table 7.3 S29CD032J/CL032J (Top Boot) Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . .22 Table 7.4 S29CD032J/CL032J (Bottom Boot) Sector and Memory Address Map . . . . . . . . . . . . . . . . .23 Table 8.1 Device Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 8 ...
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... The order number (Valid Combination) is formed by the following: S29CD032J S29CL032J 0 J Device Number/Description S29CD032J/S29CD016J (2.5 volt-only), S29CL032J/S29CL016J (3.3 volt-only Megabit (1M or 512k x 32-Bit) CMOS Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory Manufactured on 110 nm floating gate technology ...
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... S29CD-J and S29CL-J Flash Family Autoselect ID Boot Sector Packing Option Option Type ...
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... WP# ACC RESET Type Address lines for S29CD-J and S29CL-J (A18-A0 for 16 Mb and A19-A0 for 32 Mb). Input A9 supports 12V autoselect input. I/O Data input/output Input Chip Enable. This signal is asynchronous relative to CLK for the burst mode. Input Output Enable ...
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... October 11, 2012 S29CD-J_CL-J_00_B7 Erase Voltage Generator PGM Voltage Generator Chip Enable Output Enable Timer Burst Address IND/ Counter Amax-A0 S29CD-J and S29CL-J Flash Family DQ DQ0 – max Input/Output V IO Buffers Data Latch Logic Y-Decoder Y-Gating Cell Matrix ...
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... STATE RESET# CONTROL & WE# COMMAND CE# REGISTER ADV# DQ –DQ0 max A –A0 max Upper Bank Address Upper Bank X-Decoder Status Control X-Decoder Lower Bank Lower Bank Address S29CD-J and S29CL-J Flash Family OE# DQ –DQ0 max S29CD-J_CL-J_00_B7 October 11, 2012 ...
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... PQFP S29CD-J and S29CL-J Flash Family 64 DQ15 63 DQ14 62 DQ13 61 DQ12 DQ11 57 DQ10 56 DQ9 55 DQ8 54 DQ7 53 DQ6 52 ...
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... FOR DEVICES WITH LEAD PITCH OF 0. 0.076 mm FOR DEVICES WITH LEAD PITCH OF 0.50 mm. COPLANARITY IS MEASURED PER SPECIFICATION 06-500. 9. HALF SPAN (CENTER OF PACKAGE TO LEAD TIP) SHALL BE WITHIN ±0.0085". S29CD-J and S29CL-J Flash Family 0.20 MIN. FLAT SHOULDER 7˚ TYP. A 7˚ ...
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... DQ5 DQ9 A19 DQ2 DQ6 DQ10 DQ0 DQ4 DQ7 DQ8 DQ3 S29CD-J and S29CL-J Flash Family DQ20 DQ16 DQ18 IND/WAIT DQ19 OE# WE DQ17 CE ...
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... BALL COUNT WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW , e/2 BALL DIAMETER 8. N/A BALL PITCH - D DIRECTION 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALL PITCH - E DIRECTION BALLS. SOLDER BALL PLACEMENT S29CD-J and S29CL-J Flash Family ...
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... WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN BALL PITCH THE OUTER ROW e/2 SOLDER BALL PLACEMENT 8. “+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. DEPOPULATED SOLDER BALLS 9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. S29CD-J and S29CL-J Flash Family g1064 \ f16-038.12 \ 01.31.12 17 ...
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... VHDL and Verilog IBIS ORCAD 6.4 Contacting Spansion Obtain the latest list of company locations and contact information on our web site at http://www.spansion.com/About/Pages/Locations.aspx obtain the following related documents: S29CD-J and S29CL-J Flash Family S29CD-J_CL-J_00_B7 October 11, 2012 ...
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... Product Overview The S29CD-J and S29CL-J families consist and 16 Mb, 2.6 volt-only (CD-J) or 3.3 volt-only (CL-J), simultaneous read/write, dual boot burst mode Flash devices optimized for today's automotive designs. These devices are organized in 1,048,576 double words (32 Mb) or 524,288 double words (16 Mb) and are capable of linear burst read ( double words) with wraparound. (Note that 1 double word = 32 bits.) These products also offer single word programming with program/erase suspend and resume functionality ...
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... Table 7.1 S29CD016J/CL016J (Top Boot) Sector and Memory Address Map Sector x32 Address Sector Group Range (A18:A0) SA0 SG0 00000h–007FFh (Note 1) SA1 SG1 00800h–00FFFh SA2 SG2 01000h–017FFh SA3 SG3 01800h–01FFFh SA4 SG4 02000h–027FFh SA5 SG5 02800h–02FFFh ...
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... Table 7.2 S29CD016J/CL016J (Bottom Boot) Sector and Memory Address Map Sector x32 Address Sector Group Range (A18:A0) SA0 (Note 1) SG0 00000h–007FFh SA1 (Note 1) SG1 00800h–00FFFh SA2 SG2 01000h–017FFh SA3 SG3 01800h–01FFFh SA4 SG4 02000h–027FFh SA5 SG5 02800h–02FFFh ...
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... Table 7.3 S29CD032J/CL032J (Top Boot) Sector and Memory Address Map Sector x32 Address Range Sector Group (A19:A0) Bank 0 (Note 2) SA0 (Note 1) SG0 00000h–007FFh SA1 SG1 00800h–00FFFh SA2 SG2 01000h–017FFh SA3 SG3 01800h–01FFFh SA4 SG4 02000h–027FFh SA5 SG5 02800h– ...
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... Table 7.4 S29CD032J/CL032J (Bottom Boot) Sector and Memory Address Map Sector x32 Address Range Sector Group (A19:A0) Bank 0 (Note 2) SA0 (Note 3) SG0 00000h–007FFh SA1 (Note 3) SG1 00800h–00FFFh SA2 SG2 01000h–017FFh SA3 SG3 01800h–01FFFh SA4 SG4 02000h–027FFh SA5 SG5 02800h– ...
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... S29CD-J and S29CL-J Flash Family describes the required state of each Data Addresses (DQ0–DQ31 OUT High-Z High-Z High-Z X High-Z 00000001h, (protected) Sector Address ...
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... Figure 8.1 Asynchronous Read Operation Address 1 Address 2 Address for timing specifications and to for another timing diagram. I S29CD-J and S29CL-J Flash Family to read data). OE# is the IL -t and CE# has been asserted for at ACC Float Figure 18.2, Conventional in the DC Characteristics table ...
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... Mode Only Set Burst Mode Configuration Register Configuration Register Command for Synchronous Mode Asynchronous Mode (D15 = 0) Synchronous Read Mode Only S29CD-J and S29CL-J Flash Family for timing specifications. V and V Power-up on page 57 2-, 4-, 8- Double Word Linear Configuration Register Set Burst Mode ...
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... IND/ WAIT# signal is driven lists the valid combinations of the Configuration Register bits that impact the Figure 8.3 for the IND/WAIT# timing diagram. S29CD-J and S29CL-J Flash Family ) during the last transfer of data IL Output Data Sequence (Initial Access Address) 0-1 ( ...
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... CR13-CR10. See Table 8.4 Burst Initial Access Delay CR11 CR10 S29CD-J and S29CL-J Flash Family Definition Initial Burst Access (CLK cycles S29CD-J_CL-J_00_B7 October 11, 2012 D0 ...
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... Figure 8.4 Initial Burst Delay Control 2nd CLK 3rd CLK 4th CLK Three CLK Delay D0 D1 Four CLK Delay D0 Five CLK Delay Table 8.6 for the default Configuration Register settings.) The host system S29CD-J and S29CL-J Flash Family 5th CLK Command Definitions ...
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... CR12 CR11 IAD3 IAD2 IAD1 CR5 CR4 CR3 Reserve Reserve Reserve Table 8.7. In addition, when verifying sector protection, the sector address S29CD-J and S29CL-J Flash Family CR10 CR9 CR8 IAD0 DOC Reserve CR2 CR1 CR0 BL2 BL1 BL0 address pin A9 ...
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... The system must write the reset command to exit the autoselect mode and return to reading the array data. See Table 8.7 for command sequence details. Table 8.7 S29CD-J and S29CL-J Flash Family Autoselect Codes (High Voltage Method) Description Manufacturer ID: Spansion Read Cycle 1 Read Cycle 2 ...
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... A hardware reset immediately terminates the program operation; the program command sequence should be re-initiated once the device has returned to the read mode, to ensure data integrity. For the 32Mb S29CD-J and S29CL-J devices only: Please refer to the application note “Recommended Mode of Operation for Spansion S29CD032J/S29CL032J Flash Memory” ...
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... Suspend during the time-out period will be interpreted as an additional sector to erase. The device does not decode the data bus, but latches the address. (See S29CD016J Sector Erase Time-Out Functionality Application Note for further information.). The system can monitor DQ3 to determine if the sector erase timer ...
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... Figure 8.6 Erase Operation START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed for erase command sequence. for more information. Table 8.8 on page 40 S29CD-J and S29CL-J Flash Family for information on these S29CD-J_CL-J_00_B7 October 11, 2012 ...
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... The Accelerated Program command is not permitted if the Secured Silicon sector is enabled. October 11, 2012 S29CD-J_CL-J_00_B7 Write Operation Status on page 36 HH for operations other than accelerated programming or device damage HH S29CD-J and S29CL-J Flash Family for more information. (12V) HH from the ACC input, upon completion of the 35 ...
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... The device provides several bits to determine the status of a program or erase operation. The following subsections describe the function of DQ7, DQ6, DQ2, DQ5, DQ3, and RY/BY shows the requirements for the unlock bypass command sequences. S29CD-J and S29CL-J Flash Family S29CD-J_CL-J_00_B7 October 11, 2012 ...
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... See the following for more information: Data# Polling on DQ7. diagram. October 11, 2012 S29CD-J_CL-J_00_B7 Table 8.9, Write Operation Status on page 42 Figure 8.7, Data# Polling Algorithm on page 38 S29CD-J and S29CL-J Flash Family shows the outputs for shows the Data# Polling timing 37 ...
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... DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5 Figure 8.7 Data# Polling Algorithm START Read DQ7–DQ0 Addr = VA Yes DQ7 = Data DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA Yes DQ7 = Data? No FAIL S29CD-J and S29CL-J Flash Family PASS S29CD-J_CL-J_00_B7 October 11, 2012 ...
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... Thus, both status bits are required for sector and mode information. Refer to Table 8.8 to compare outputs for DQ2 and DQ6. See October 11, 2012 S29CD-J_CL-J_00_B7 DQ6: Toggle Bit I on page 39 S29CD-J and S29CL-J Flash Family for additional information. for additional information. 39 ...
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... S29CD-J and S29CL-J Flash Family for more on the Toggle Bit Algorithm. and DQ2 toggles, does not toggle. toggles, also toggles. ...
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... Figure 8.8 Toggle Bit Algorithm START Read Byte (DQ0-DQ7) Address = VA (Note 1) Read Byte (DQ0-DQ7) Address = VA No DQ6 = Toggle? Yes No DQ5 = 1? Yes Read Byte Twice (DQ0-DQ7) (Notes 1, 2) Adrdess = VA No DQ6 = Toggle? Yes FAIL S29CD-J and S29CL-J Flash Family PASS 41 ...
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... Table 8.9 Write Operation Status DQ7 (Note 2) DQ6 DQ7# Toggle 0 Toggle 1 No toggle Data Data DQ7# Toggle for more information. S29CD-J and S29CL-J Flash Family (during Embedded Algorithms). The READY after the RH level since the output Figure 18.2, Figure 18.6, DQ5 DQ2 (Note 1) DQ3 ...
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... This section describes the various methods of protecting data stored in the memory array. An overview of these methods in shown in October 11, 2012 S29CD-J_CL-J_00_B7 Table 8.10 Reset Command Timing Description Figure S29CD-J and S29CL-J Flash Family before it returns to the read or erase- RR Max. Unit 250 ns 9.1. ...
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... Memory Array Sector Group 0 Sector Group 1 Sector Group 2 Sector Group N-2 Sector Group N-1 4 Sector Group for S29CD016J/CL016J, 31 for S29CD032J/CL032J Figure 9.1 Advanced Sector Protection/Unprotection Software Methods Password Method Persistent Method 64-bit Password ...
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... PPB over-erasure the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-out without programming or erasing the PPB. October 11, 2012 S29CD-J_CL-J_00_B7 49. 75. S29CD-J and S29CL-J Flash Family Persistent Protection Bits on page 45 to Command 45 ...
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... OR wait 100 µs Write 0x48 to SG+WP Read from SG+WP NO DQ0 = 1? YES Done S29CD-J and S29CL-J Flash Family Note: Reads from the small bank at this point return the status of the operation, not read array data. YES S29CD-J_CL-J_00_B7 October 11, 2012 ...
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... OR wait 20 ms Write 0x40 to WP Read from WP NO DQ0 = 0? YES YES Done S29CD-J and S29CL-J Flash Family Note: Reads from the small bank at this point return the status of the operation, not read array data. 47 ...
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... Table 9.1 Sector Protection Schemes 0 Unprotected—PPB and DYB are changeable 1 Unprotected—PPB not changeable, DYB is changeable 0 0 Protected—PPB and DYB are changeable Protected—PPB not changeable, DYB is changeable 1 S29CD-J and S29CL-J Flash Family Sector State S29CD-J_CL-J_00_B7 October 11, 2012 ...
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... RESET and V Power-up on page 57 CE while OE logical one (V IL S29CD-J and S29CL-J Flash Family on the WP# pin, the The system must provide the LKO is greater than LKO WE initiate a write cycle, ...
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... This prevents resuming either programming or erasure on the Secured Table 10.1 Secured Silicon Sector Addresses Sector Size (Bytes) 256 256 S29CD-J and S29CL-J Flash Family Table 10.1 for Address Range 00000h-0003Fh (16 Mb and 32 Mb) FFFC0h–FFFFFh (32 Mb) 7FFC0h–7FFFFh (16 Mb) S29CD-J_CL-J_00_B7 October 11, 2012 ...
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... Table 20.2, Sector Protection Command Definitions for address and data requirements for both command sequences. Table 10.1, Secured Silicon Sector Addresses on page ) for read access before it is ready to read data represents the standby current specification. S29CD-J and S29CL-J Flash Family Table 20.1, Memory 50. 51 ...
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... V, the device draws CMOS standby current (I SS ±0.2 V, the standby current is greater. and V power up is required to guarantee proper device initialization output from the device is disabled. The outputs are placed in the high IH S29CD-J and S29CL-J Flash Family 52for further ). If RESET# is held at CC4 S29CD-J_CL-J_00_B7 October 11, 2012 ...
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... Electrical Specifications 13.1 Absolute Maximum Ratings Storage Temperature, Plastic Packages Ambient Temperature with Power Applied (Note 1) for 2.6 V devices (S29CD- (Note 1) for 3.3 V devices (S29CL- ACC, A9, and RESET# Address, Data, Control Signals Output Short Circuit Current Notes 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input at I/O pins may overshoot ...
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... Table 14.1 Operating Ranges Parameter Industrial Devices ) A Extended Devices V for 2.6V regulated voltage range (S29CD-J devices for 3.3V regulated voltage range (S29CL-J devices (S29CD-J devices (S29CL-J devices) IO Table 15.1 DC Characteristic, CMOS Compatible Test Conditions ...
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... October 11, 2012 S29CD-J_CL-J_00_B7 Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 1000 1500 2000 Time in ns Figure 15.2 Typical I vs. Frequency CC1 2 3 Frequency in MHz S29CD-J and S29CL-J Flash Family 2500 3000 3500 4000 2 ...
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... Table 17.2 Key to Switching Waveforms Inputs Changing from Changing from Don’t Care, Any Change Permitted Does Not Apply Figure 17.1 Input Waveforms and Measurement Levels Measurement Level IO S29CD-J and S29CL-J Flash Family L All Options 1 TTL gate 30 5 0.0V – ...
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... Table 18.1 V and V Power- Description V Setup Time CC V Setup Time IO RESET# Low Hold Time Figure 18.1 V and V Power-up Diagram VCS t VIOS t RSTH S29CD-J and S29CL-J Flash Family Test Setup Speed Unit Min 50 µs Min 50 µs Min 50 µs 57 ...
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... OE OE (Note 1) Read Toggle and Data# Polling (Note 1) Figure 18.2 Conventional Read Operations Timings t RC Addresses Stable t ACC OEH t CE High Z S29CD-J and S29CL-J Flash Family Speed Options 75 MHz 66 MHz 56 MHz 40 MHz 0J/1J Min 54 Max 54 Max 54 Max 20 Max 10 Min 2 ...
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... Configuration Register. 2. Refer to Table 18.5 for write timing parameters. October 11, 2012 S29CD-J_CL-J_00_B7 Figure 18.3 Asynchronous Command Write Timing Stable Address Valid Data WEH t OEP S29CD-J and S29CL-J Flash Family ...
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... Max (Note 2) Min Max Min Max Max Max Min Min Max Min (Note 2) Max (Note 2) Max Min (Note 1) Max Min (Note 2) Max Min Min Min S29CD-J and S29CL-J Flash Family Speed Options 66 MHz, 56 MHz, 40 MHz 0J/ 1.5 7.5 8.5 9.5 10 ...
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... OE Figure 18.5 Synchronous Command Write/Read Timing t CES t ADVCS t ADVP t AS Valid Address Valid Address ADVCH Data In t WADVH2 t WADVH1 WADVS S29CD-J and S29CL-J Flash Family t CEZ OEZ t INDS t INDH t EHQZ Data Out ...
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... Note) (See Note) Figure 18.6 RESET# Timings READY2 Reset Timing to Bank NOT Executing Embedded Algorithm Reset Timing to Bank Executing Embedded Algorithm t READY t RP S29CD-J and S29CL-J Flash Family Test All Speed Setup Options Unit Max 11 µs Min 500 ns Min 500 ns ...
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... Setup Time (Note 1) CC Recovery Time from RY/BY# (Note 1) RY/BY# Delay After WE# Rising Edge (Note 1) WP# Setup to WE# Rising Edge with Command WP# Hold after RY/BY# Rising Edge (Note 1) for more information. S29CD-J and S29CL-J Flash Family BUSY t WPRH All Speed Options Unit Min ...
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... Figure 18.8 Program Operation Timings WPH A0h t BUSY is the true data at the program address. S29CD-J and S29CL-J Flash Family Read Status Data (last two cycles WHWH1 Status D OUT t RB S29CD-J_CL-J_00_B7 October 11, 2012 ...
Page 65
... Figure 18.10 Back-to-back Cycle Timings t RC Valid RA t ACC OEH GHWL t WPH Valid Out t SR/W Read Cycle S29CD-J and S29CL-J Flash Family Read Status Data WHWH2 In Complete Progress Valid PA Valid PA t CPH t CP Valid Valid In In ...
Page 66
... Status Data ACC Valid Status Valid Status (first read) (second read) S29CD-J and S29CL-J Flash Family High Z Valid Data True High Z Valid Data True VA VA Valid Status Valid Data (stops toggling) S29CD-J_CL-J_00_B7 October 11, 2012 ...
Page 67
... Data polling requires burst access time delay. October 11, 2012 S29CD-J_CL-J_00_B7 Enter Erase Suspend Program Erase Suspend Erase Suspend Read Program Status Data S29CD-J and S29CL-J Flash Family Erase Resume Erase Suspend Erase Erase Read Complete t OE Status Data 67 ...
Page 68
... Command for sector protect is 68h. Command for sector unprotect is 60h. *** Command for sector protect verify is 48h. Command for sector unprotect verify is 40h Valid* 60h/68h** 40h/48h*** Sector Protect: 150 µs Sector Unprotect S29CD-J and S29CL-J Flash Family Valid* Valid* Verify Status S29CD-J_CL-J_00_B7 October 11, 2012 ...
Page 69
... Notes 1. Not 100% tested. 2. See Command Definitions on page 75 October 11, 2012 S29CD-J_CL-J_00_B7 Table 18.6 Alternate CE# Controlled Erase/Program Operations Description (Note 1) (Note 2) (Note 2) for more information. S29CD-J and S29CL-J Flash Family All Speed Options Min 65 Min 0 Min 45 Min 35 Min ...
Page 70
... WPH t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase S29CD-J and S29CL-J Flash Family Data# Polling PA DQ7# D OUT = data written to the device. OUT S29CD-J_CL-J_00_B7 October 11, 2012 ...
Page 71
... Additionally, programming typicals assume checkerboard CC Table 18.8 PQFP and Fortified BGA Pin Capacitance Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance S29CD-J and S29CL-J Flash Family Comments Excludes 00h programming prior to erasure (Note 4) Excludes system level overhead (Note 5) Table 20.1 and Table 20 ...
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... Max. timeout for word/doubleword program 2 0000h Max. timeout for buffer write 2 0007h Max. timeout per individual block erase 2 0000h Max. timeout for full chip erase 2 S29CD-J and S29CL-J Flash Family 19.3. In order to terminate reading CFI Table 19.1- Description Description pin present) PP pin present) ...
Page 73
... CS119 Erase Suspend (1 byte Not Supported 0002h Read Only Read and Write Sector Protect (1 byte) 0001h 00 = Not Supported Number of sectors in per group Temporary Sector Unprotect 0000h 00h = Not Supported, 01h = Supported S29CD-J and S29CL-J Flash Family Description N Description 73 ...
Page 74
... Bank 1 Region Information (1 byte) 0017h XX = Number of Sectors in Bank 1 Bank 2 Region Information (1 byte) 0037h XX = Number of Sectors in Bank 2 Bank 3 Region Information (1 byte) 0000h XX = Number of Sectors in Bank 3 Bank 4 Region Information (1 byte) 0000h XX = Number of Sectors in Bank 4 S29CD-J and S29CL-J Flash Family Description S29CD-J_CL-J_00_B7 October 11, 2012 ...
Page 75
... Command is ignored during any Embedded Program, Embedded Erase, or Suspend operation. 15. The Unlock Bypass Entry command is required prior to any Unlock Bypass operation. The Unlock Bypass Reset command is required to return to the for more information. read mode. S29CD-J and S29CL-J Flash Family Fourth Fifth Sixth Data Addr ...
Page 76
... PPBs. 11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not set. 12. The status of additional PPBs and DYBs may be read (following the fourth cycle) without reissuing the entire command sequence. S29CD-J and S29CL-J Flash Family Fourth Fifth Sixth ...
Page 77
... INDH changed t OEH WEH WPH and t from figure. WADVH WCKS BUSY (OE# High Pulse) OEP from table. Added t and t OES WADVS WCKS S29CD-J and S29CL-J Flash Family Ratings to reflect 16 Mb and Changed CLKH CL CLKL OEP . 77 ...
Page 78
... Changed cycling endurance specification to typical. Performance Characteristics Changed t Ordering Information Added quantities to packing type descriptions, restructured table for easier reference. S29CD-J and S29CL-J Flash Family Autoselect Codes (High Voltage In table, modified description of read cycle 3 DQ7–DQ0. Method) DQ6 and DQ2 Indications In table, corrected third column heading Section 8 ...
Page 79
... SS for S29CL mA. CCB with separate values for 16Mb and 32Mb. BDH parameter to table. WADVS . WADVS description. AH Min to 11.75 ns. AH value. AH value. AH parameter. WADVS S29CD-J and S29CL-J Flash Family , for 75 MHz device. ACC and t INDS CLKL AAVH WADVH1 79 ...
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... Mb and 32 Mb. DH value differences between CL-J and CD-J. IHCLK to timing diagram for bank not executing READY2 and t GHWL WEH measurement to be from the falling edge of WE#. AH S29CD-J and S29CL-J Flash Family , t , and t set up to Min READY2 RP READY3 CCQ IO ...
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... Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. October 11, 2012 S29CD-J_CL-J_00_B7 ® , the Spansion logo, MirrorBit S29CD-J and S29CL-J Flash Family ® ® , MirrorBit Eclipse™, ORNAND™ and 81 ...