S29CD016G SPANSION, S29CD016G Datasheet - Page 63

• Manufacturer Part Number: S29CD016G
• Description: 16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode / Dual Boot / Simultaneous Read/Write Flash Memory
• Manufacturer: SPANSION

November 5, 2004 S29CD016_00_A4
DQ2: Toggle Bit II
Reading Toggle Bits DQ6/DQ2
If a program address falls within a protected sector, DQ6 toggles for approxi-
mately 1 µs after the program command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
Table 21 on page 65
page 64
ing Toggle Bits DQ6/DQ2” on page 63
page 80
differences between DQ2 and DQ6 in graphical form. See also the subsection on
“DQ2: Toggle Bit
chronous toggle bit status.
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system performs two immediately consecutive reads at
addresses within those sectors that were selected for erasure. (For asynchronous
mode, either OE# or CE# can be used to control the read cycles. For synchronous
mode, ADV# is used.) But DQ2 cannot distinguish whether the sector is actively
erasing or is erase-suspended. DQ6, by comparison, indicates whether the device
is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors
are selected for erasure. Thus, both status bits are required for sector and mode
information. Refer to
Figure 7, on page 64
section
also the
the toggle bit timing diagram.
tween DQ2 and DQ6 in graphical form.
diagram for synchronous DQ2 toggle bit status.
Refer to
tem initially begins reading toggle bit status, it must perform two immediately
consecutive reads of DQ7–DQ0 to determine whether a toggle bit is toggling. Typ-
ically, the system would note and store the value of the toggle bit after the first
read. After the second read, the system would compare the new value of the tog-
gle bit with the first. If the toggle bit is not toggling, the device completed the
program or erase operation. The system can read array data on DQ7–DQ0 on the
following read cycle.
However, if after the initial two immediately consecutive read cycles, the system
determines that the toggle bit is still toggling, the system also should note
whether the value of DQ5 is high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer
toggling, the device successfully completed the program or erase operation. If it
is still toggling, the device did not complete the operation successfully, and the
system must write the reset command to return to reading array data.
“Reading Toggle Bits DQ6/DQ2” on page 63
“DQ6: Toggle Bit I” on page 62
shows the toggle bit algorithm in flowchart form, and the section
shows the toggle bit timing diagrams.
Figure 26, on page 81
A d v a n c e
II”.
Table 21 on page 65
shows the outputs for Toggle Bit I on DQ6.
Figure 25, on page 80
shows the toggle bit algorithm in flowchart form, and the
I n f o r m a t i o n
Figure 26, on page 81
for the following discussion. Whenever the sys-
S29CD016G
subsection.
Figure 27, on page 81
explains the algorithm.
to compare outputs for DQ2 and DQ6.
shows the timing diagram for syn-
Figure 25, on page 80
Figure 25, on page 80
explains the algorithm. See
shows the differences be-
shows the timing
Figure 25, on
Figure 7, on
shows the
“Read-
shows
63