S29CD016G SPANSION, S29CD016G Datasheet - Page 43

• Manufacturer Part Number: S29CD016G
• Description: 16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode / Dual Boot / Simultaneous Read/Write Flash Memory
• Manufacturer: SPANSION

Command Definitions
November 5, 2004 S29CD016_00_A4
Reading Array Data in Non-burst Mode
Reading Array Data in Burst Mode
Writing specific address and data commands or sequences into the command
register initiates device operations. Tables 8-9 define the valid register command
sequences. Writing incorrect address and data values or writing them in the
improper sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. The device is also ready to read array
data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase
Suspend mode. The system can read array data using the standard read timings,
except that if it reads at an address within erase-suspended sectors, the device
outputs status data. After completing a programming operation in the Erase Sus-
pend mode, the system may once again read array data with the same exception.
See
mation on this mode.
The system must issue the reset command to re-enable the device for reading
array data if DQ5 goes high, or while in the autoselect mode.
See also
information. See
more information on this mode.
The device is capable of very fast Burst mode read operations. The configuration
register sets the read configuration, burst order, frequency configuration, and
burst length.
Upon power on, the device defaults to the asynchronous mode. In this mode,
CLK, and ADV# are ignored. The device operates like a conventional Flash device.
Data is available t
come asserted. The device enters the burst mode by enabling synchronous burst
reads in the configuration register. The device exits burst mode by disabling syn-
chronous burst reads in the configuration register. (See
on page
reset (power on reset) terminates the Burst mode.
The device contains the regular control pins, i.e. Chip Enable (CE#), Write Enable
(WE#), and Output Enable (OE#) to control normal read and write operations.
Moreover, three additional control pins were added to allow easy interface with
minimal glue logic to a wide range of microprocessors / microcontrollers for high
performance Burst read capability. These additional pins are Address Valid
(ADV#) and Clock (CLK). CE#, OE#, and WE# are asynchronous (relative to
CLK). The Burst mode read operation is a synchronous operation tied to the edge
of the clock. The microprocessor / microcontroller supplies only the initial ad-
dress, all subsequent addresses are automatically generated by the device with
a timing defined by the Configuration Register definition. The Burst read cycle
consists of an address phase and a corresponding data phase.
“Sector Erase and Program Suspend Command” on page 49
43). The RESET# command does not terminate the Burst mode. System
“Asynchronous Read Operation (Non-Burst)” on page 19
A d v a n c e
“AC Characteristics” on page 70
“Sector Erase and Program Resume Command” on page 51
ACC
/t
CE
nanoseconds after address becomes stable, CE# be-
I n f o r m a t i o n
S29CD016G
for timing diagrams.
“Command Definitions”
for more infor-
for more
for
43