S29CD016G SPANSION, S29CD016G Datasheet - Page 23

• Manufacturer Part Number: S29CD016G
• Description: 16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode / Dual Boot / Simultaneous Read/Write Flash Memory
• Manufacturer: SPANSION

November 5, 2004 S29CD016_00_A4
Note: Operation is shown for the 32-bit data bus. Figure shown with 3-CLK initial access
delay configuration, linear address, 4-double-word burst, output on rising CLK edge, data hold for 1-CLK, IND/
WAIT# asserted on the last transfer before wrap-around
IND/WAIT#
Addresses
Figure 2. End of Burst Indicator (IND/WAIT#) Timing for Linear 4-Double-Word Burst Operation
ADV#
Data
OE#
CE#
CLK
Burst Access Timing Control
In addition to the IND/WAIT# signal control, burst controls exist in the Control
Register for initial access delay, delivery of data on the CLK edge, and the length
of time data is held.
Initial Burst Access Delay Control
The device contains options for initial access delay of a burst access. The initial
access delay has no effect on asynchronous read operations.
Burst Initial Access Delay is defined as the number of clock cycles that must
elapse from the first valid clock edge after ADV# assertion (or the rising edge of
ADV#) until the first valid CLK edge when the data is valid.
The burst access is initiated and the address is latched on the first rising CLK edge
when ADV# is active or upon a rising ADV# edge, whichever comes first.
8
V
V
IH
IL
shows the initial access delay configurations.)
CR13
Address 1
0
0
0
0
A d v a n c e
CR12
0
0
0
0
Table 8. Burst Initial Access Delay (Sheet 1 of 2)
Address 1 Latched
3 Clock Delay
CR11
0
0
1
1
I n f o r m a t i o n
CR10
0
1
0
1
S29CD016G
Invalid
Initial Burst Access
(CLK cycles)
D1
2
3
4
5
D2
(Table
D3
D0
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