MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 13

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

Commands
able commands. This is followed by a verbal descrip-
tion of each command. Two additional Truth Tables
TRUTH TABLE 1 – COMMANDS
(Note: 1)
TRUTH TABLE 1A – DM OPERATION
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
NAME (FUNCTION)
Write Enable
Write Inhibit
Truth Table 1 provides a quick reference of avail-
10. Used to mask write data; provided coincident with the corresponding data.
2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;
3. BA0-BA1 provide bank address and A0-A11 provide row address.
4. BA0-BA1 provide bank address; A0-Ai provide column address (where i = 8 for x16, 9 for x8, and 9, 11 for x4); A10 HIGH
5. A10 LOW: BA0-BA1 determine which bank is precharged.
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
9. DESELECT and NOP are functionally interchangeable.
BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A11 provide the
op-code to be written to the selected mode register.
enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
A10 HIGH: all banks are precharged and BA0-BA1 are “Don’t Care.”
bursts with auto precharge enabled and for WRITE bursts.
13
appear following the Operation section; these tables
provide current state/next state information.
CS# RAS# CAS# WE#
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
L
L
L
L
L
L
L
L
H
X
H
H
H
L
L
L
L
128Mb: x4, x8, x16
H
H
H
H
X
L
L
L
L
H
H
H
H
X
L
L
L
L
DM
H
DDR SDRAM
L
Bank/Row
Op-Code
Bank/Col
Bank/Col
PRELIMINARY
ADDR
Code
Valid
DQs
X
X
©2001, Micron Technology, Inc.
X
X
X
NOTES
NOTES
6, 7
10
10
9
9
3
4
4
8
5
2