MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 39

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

TRUTH TABLE 3 – CURRENT STATE BANK n – COMMAND TO BANK n
(Notes: 1-6; notes appear below and on next page)
NOTE:
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
CURRENT STATE CS# RAS# CAS# WE#
1. This table applies when CKE
2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the com-
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT
Row Active
Precharge
Precharge
Disabled)
Disabled)
met (if the previous state was self refresh).
mands shown are those allowed to be issued to that bank when in that state). Exceptions are covered in
the notes below.
or NOP commands, or allowable commands to the other bank should be issued on any clock edge occur-
ring during these states. Allowable commands to the other bank are determined by its current state and
Truth Table 3, and according to Truth Table 4.
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends
(Auto-
(Auto-
Write
Read
Any
Idle
Row Activating: Starts with registration of an ACTIVE command and ends when
Write w/Auto-
Read w/Auto-
Precharging: Starts with registration of a PRECHARGE command and ends when
Row Active: A row in the bank has been activated, and
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Idle: The bank has been precharged, and
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
and no register accesses are in progress.
terminated or been terminated.
terminated or been terminated.
t
Once
when
when
RP is met, the bank will be in the idle state.
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
t
t
t
RCD is met, the bank will be in the “row active” state.
n-1
RP has been met. Once
RP has been met. Once
was HIGH and CKE
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
WRITE (select column and start WRITE burst)
READ (select column and start READ burst)
COMMAND/ACTION
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
READ (select column and start READ burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (truncate READ burst, start PRECHARGE)
BURST TERMINATE
WRITE (select column and start new WRITE burst)
PRECHARGE (truncate WRITE burst, start PRECHARGE)
n
39
is HIGH (see Truth Table 2) and after
t
t
RP is met, the bank will be in the idle state.
RP is met, the bank will be in the idle state.
t
RP has been met.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCD has been met. No data bursts/accesses
128Mb: x4, x8, x16
t
RCD is met.
DDR SDRAM
t
t
XSNR has been
RP is met. Once
PRELIMINARY
©2001, Micron Technology, Inc.
NOTES
10, 12
10, 11
8, 11
10
10
10
10
7
7
8
8
9