MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 50

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

NOTES
1. All voltages referenced to V
2. Tests for AC timing, I
3. Outputs measured with equivalent load:
4. AC timing and I
5. The AC and DC input level specifications are as
6. V
7. V
8. V
9. The value of V
10. I
11. Enables on-chip refresh and address counters.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
DC characteristics may be conducted at nominal
reference/supply voltage levels, but the related
specifications and device operation are guaran-
teed for the full voltage range specified.
swing of up to 1.5V in the test environment, but
input timing is still referenced to V
crossing point for CK/CK#), and parameter
specifications are guaranteed for the specified
AC input levels under normal use conditions.
The minimum slew rate for the input signals
used to test the device is 1V/ns in the range
between V
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in
that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
ting device and to track variations in the DC
level of the same. Peak-to-peak noise (non-
common mode) on V
percent of the DC value. Thus, from V
V
additional ±25mV for AC noise. This measure-
ment is to be taken at the nearest V
capacitor.
system supply for signal termination resistors, is
expected to be set equal to V
variations in the DC level of V
the input level on CK and the input level on CK#.
V
variations in the DC level of the same.
rates. Specified values are obtained with
minimum cycle time at CL = 2 for -75Z and -8,
CL = 2.5 for -75 with the outputs open.
DD
REF
REF
TT
ID
DD
is the magnitude of the difference between
is not applied directly to the device. V
Q/2 of the transmitting device and must track
is dependent on output loading and cycle
is expected to equal V
is allowed ±25mV for DC error and an
IL
(
AC
Output
(V
) and V
IX
OUT
DD
and V
)
tests may use a V
DD
REF
IH
V
MP
(
, and electrical AC and
TT
AC
may not exceed ±2
50
30pF
are expected to equal
).
DD
Reference
Point
SS
Ω
REF
.
Q/2 of the transmit-
REF
and must track
.
REF
REF
IL
-to-V
(or to the
by-pass
DD
Q/2,
TT
IH
is a
50
12. I
13. This parameter is sampled. V
14. Command/Address input slew rate = 0.5V/ns.
15. The CK/CK# input reference level (for timing
16. Inputs are not recognized as valid until V
17. The output timing reference level, as measured at
18.
19. The maximum limit for this parameter is not a
20. This is not a device limit. The device will operate
21. It is recommended that DQS be valid (HIGH or
22. MIN (
properly initialized, and is averaged at the
defined cycle rate.
V
T
peak) = 0.2V. DM input is grouped with I/O
pins, reflecting the fact that they are matched in
loading.
For -75 with slew rates 1V/ns and faster,
t
than 0.5V/ns, timing must be derated:
additional 50ps per each 100mV/ns reduction in
slew rate from the 500mV/ns.
that is, it remains constant. If the slew rate
exceeds 4.5V/ns, functionality is uncertain.
referenced to CK/CK#) is the point at which CK
and CK# cross; the input reference level for
signals other than CK/CK# is V
stabilizes. Exception: during the period before
V
LOW.
the timing reference point indicated in Note 3, is
V
t
time windows as valid data transitions. These
parameters are not referenced to a specific
voltage level, but specify when the device output
is no longer driving (HZ) or begins driving (LZ).
device limit. The device will operate with a
greater value for this parameter, but system
performance (bus turnaround) will degrade
accordingly.
with a negative value, but system performance
could be degraded due to bus turnaround.
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously
in progress on the bus. If a previous WRITE was
in progress, DQS could be HIGH during this
time, depending on
smallest multiple of
absolute value for the respective parameter.
(MAX) for I
multiple of
absolute value for
IH are reduced to 900ps. If the slew rate is less
HZ and
DD
A
DD
REF
TT
= 25°C, V
.
specifications are tested after the device is
Q = +2.5V ±0.2V, V
stabilizes, CKE ≤ 0.3 x V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RC or
t
LZ transitions occur in the same access
DD
t
CK that meets the maximum
OUT
t
RFC) for I
measurements is the largest
(
DC
128Mb: x4, x8, x16
) = V
t
RAS.
t
t
CK that meets the minimum
DQSS.
REF
DD
DD
Q/2, V
= V
measurements is the
DDR SDRAM
DD
DD
SS
REF
Q is recognized as
t
, f = 100 MHz,
PRELIMINARY
= +2.5V ±0.2V,
IH has 0ps added,
OUT
.
©2001, Micron Technology, Inc.
(peak to
t
IS has an
t
IS and
REF
t
RAS