MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 63

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MT46V16M8TG-8L

Manufacturer Part Number
MT46V16M8TG-8L
Description
DOUBLE DATA RATE DDR SDRAM
Manufacturer
MICRON [Micron Technology]
Datasheet
x4: A0-A9, A11
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
COMMAND
x16: A9, A11
x16: A0-A8
x8: A0-A9
BA0, BA1
Case 1:
Case 2:
x8: A11
NOTE: 1. DO n = data-out from column n; subsequent elements are provided in the programmed order.
DQS
DQ
DQS
DQ
CK#
CKE
A10
DM
CK
1
1
5
t
t
AC
AC
(MIN)
(MAX)
2. Burst length = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T5.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.
7. The PRECHARGE command can only be applied at T5 if
8. Refer to figure 27, 27A, and 28 for detailed DQS and DQ timing.
and
t
t
and
IS
IS
NOP 6
T0
t
t
t
DQSCK
t
DQSCK
IH
IH
(MIN)
(MAX)
t
Bank x
t
IS
IS
ACT
T1
RA
RA
RA
BANK READ – WITHOUT AUTO PRECHARGE
t
t
IH
IH
t
CK
t
t
RAS 7
RCD
t
RC
NOP 6
T2
t
CH
t
CL
t
Bank x
READ 2
Col n
IS
3
T3
t
t
RAS minimum is met.
IH
CL = 2
t
LZ
63
(MIN)
NOP 6
T4
t
RPRE
t
LZ
(MIN)
t
RPRE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ALL BANKS
ONE BANK
Bank x 4
PRE
T5
7
DO
t
n
DQSCK
t
DQSCK
DO
n
t
AC
T5n
t
AC
(MIN)
(MIN)
(MAX)
128Mb: x4, x8, x16
t
(MAX)
RP
NOP 6
T6
T6n
t
t
HZ
RPST
DDR SDRAM
t
(MAX)
RPST
NOP 6
PRELIMINARY
T7
TRANSITIONING DATA
DON’T CARE
©2001, Micron Technology, Inc.
Bank x
T8
ACT
RA
RA
RA

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