MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 47

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

CAPACITANCE (x16)
(Note: 13; notes appear on pages 50–53)
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
I
(Notes: 1–5, 10, 12, 14; notes appear on pages 50–53) (0°C ≤ T
OPERATING CURRENT: Four bank interleaving READs (BL=4) with
inputs change only during Active, READ, or WRITE commands.
PARAMETER/CONDITION
OPERATING CURRENT: One bank; Active-Precharge;
t
cyle; Address and control inputs changing once every two clock cycles;
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2;
t
inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All banks idle;
CKE = HIGH; Address and other control inputs changing once per
clock cycle. V
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank;
Active-Precharge;
inputs changing twice per clock cycle; Address and other control
inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle;
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle;
t
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE ≤ 0.2V
auto precharge,
DD
CK =
RC =
CK =
PARAMETER
Delta Input/Output Capacitance: DQ0-DQ7, LDQS, LDM
Delta Input/Output Capacitance: DQ8-DQ15, UDQS, UDM
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
Input/Output Capacitance: DQs, LDQS, UDQS, LDM, UDM
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
Input Capacitance: CKE
SPECIFICATIONS AND CONDITIONS (x16)
t
t
t
RC (MIN);
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
CK (MIN); DQ, DM, and DQS inputs changing once per clock
t
CK =
IN
= V
t
t
CK =
RC =
t
t
CK (MIN); I
RC =
REF
t
t
CK =
CK =
t
t
for DQ, DQS, and DM
RC (MIN);
CK (MIN); I
t
RAS (MAX);
t
t
CK (MIN); CKE = LOW;
CK (MIN); CKE = LOW
OUT
= 0mA
t
OUT
CK =
t
= 0mA; Address and control
CK =
t
CK (MIN); Address and control
t
CK (MIN); DQ, DM, and DQS
t
t
Standard
Low power (L)
t
RC =
RC = 15.625µs
t
CK =
RC =
t
47
RFC (MIN)
t
t
CK (MIN);
RC (MIN);
A
≤ +70°C; V
SYMBOL
I
I
I
I
I
I
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
I
DD
I
I
I
I
I
DD
DD
DD
DD
I
DD
DD
DD
DD
DD
DD
DD
4W
3N
2P
3P
4R
2F
5
6
7
7
8
0
1
SYMBOL
DD
DC
DC
DC
DC
C
C
C
C
Q = +2.5V ±0.2V, V
-75/-75Z
IO
IOU
I
I
I
IOL
1
2
3
I
I
TBD
TBD
TBD
1
2
TBD
TBD
TBD
TBD
TBD
250
3
5
2
1
128Mb: x4, x8, x16
MAX
MIN
4.0
2.0
2.0
2.0
–
–
–
–
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
220
-8
3
5
3
1
MAX
0.50
0.50
0.50
0.25
DDR SDRAM
5.0
3.0
3.0
3.0
UNITS
DD
PRELIMINARY
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
= +2.5V ±0.2V)
©2001, Micron Technology, Inc.
UNITS
p F
p F
p F
p F
p F
p F
p F
p F
23, 32, 50
23, 32, 50
22, 48
22, 48
22, 50
27, 50
NOTES
22,48
22,49
51
47
22
11
11
NOTES
24
24
29
29