AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 18

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

18
4
4.1
Am5
on-chip memory management and cache memory units.
The instruction set includes the complete 486 micropro-
cessor instruction set along with extensions to serve the
new extended applications. All software written for the
486 microprocessor and previous members of the x86
architectural family can run on the Am5
cessor without modification.
The on-chip Memory Management Unit (MMU) is com-
pletely compatible with the 486 MMU. The MMU in-
cludes a segmentation unit and a paging unit.
Segmentation allows management of the logical ad-
dress space by providing easy data and code relocati-
bility and efficient sharing of global resources. The
paging mechanism operates beneath segmentation and
is transparent to the segmentation process. Paging is
optional and can be disabled by system software. Each
segment can be divided into one or more 4-Kbyte seg-
ments. To implement a virtual memory system, the
Am5
all page and segment faults.
4.2
Memory is organized into one or more variable length
segments, each up to 4 Gbytes (2
can have attributes associated with it, including its lo-
cation, size, type (i.e., stack, code, or data), and protec-
tion characteristics. Each task on a microprocessor can
have a maximum of 16,381 segments, each up to 4
Gbytes. Thus, each task has a maximum of 64 Tbytes
of virtual memory.
The segmentation unit provides four levels of protection
for isolating and protecting applications and the operat-
ing system from each other. The hardware-enforced
protection allows high-integrity system designs.
4.3
The Am5
tion: Real Address mode (Real mode), Virtual 8086 Ad-
dress mode (Virtual mode), Protected Address mode
(Protected mode), and System Management mode
(SMM).
4.3.1 Real Mode
In Real mode, the Am5
a fast 8086. Real mode is required primarily to set up
the processor for Protected mode operation.
4.3.2 Virtual Mode
In Virtual mode, the processor appears to be in Real
mode, but can use the extended memory accessing of
Protected mode.
X
X
AMD
86 microprocessors use a 32-bit architecture with
86 microprocessor supports full restartability for
FUNCTIONAL DESCRIPTION
Overview
Memory
Modes of Operation
X
86 microprocessor has four modes of opera-
X
86 microprocessor operates as
32
bytes). A segment
X
86 micropro-
Am5
X
PRELIMINARY
86 Microprocessor
4.3.3 Protected Mode
Protected mode provides access to the sophisticated
memory management paging and privilege capabilities
of the processor.
4.3.4 System Management Mode
SMM is a special operating mode described in detail in
Section 7.
4.4
The Am5
architecture of the standard 486 cache implementation.
This architectural enhancement improves not only CPU
performance, but total system performance.
4.4.1 Write-Through Cache
The standard 486DX-type write-through cache architec-
ture is characterized by the following:
The write-through cache implementation forces all
writes to flow through to the external bus and back to
main memory. Consequently, the write-through cache
generates a large amount of bus traffic on the external
data bus.
4.4.2 Write-Back Cache
The microprocessor write-back cache architecture is
characterized by the following:
The write-back cache feature significantly reduces the
amount of bus traffic on the external bus; however, it
also adds complexity to the system design to maintain
memory coherency. The write-back cache requires en-
External read accesses are placed in the cache if
they meet proper caching requirements.
Subsequent reads to the data in the cache are made
if the address is stored in the cache tag array.
Write operations to a valid address in the cache are
updated in the cache and to external memory. This
data writing technique is called write-through .
External read accesses are placed in the cache if
they meet proper caching requirements.
Subsequent reads to the data in the cache are made
if the address is stored in the cache tag array.
Write operations to a valid address in the cache that
is in the write-through (shared) state is updated in
the cache and to external memory.
Write operations to a valid address in the cache that
is in the write-back (exclusive or modified) state is
updated only in the cache. External memory is not
updated at the time of the cache update.
Modified data is written back to external memory
when the modified cache line is being replaced with
a new cache line (copy-back operation) or an exter-
nal bus master has snooped a modified cache line
(write-back).
Cache Architecture
X
86 microprocessor family supports a superset