AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 29

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

Step 8 As an example, AHOLD is now removed. In the
Step 9 The write-back access is finished when BLAST
Step 10 In the clock cycle after the final write-back
The status of the snooped and written-back line is now
either shared (INV = 0) or is changed to invalid (INV = 1).
4.8.6 Reordering of Write-Backs (AHOLD) with
As seen previously, the Bus Interface Unit (BIU) com-
pletes the processor-initiated access first if the snooping
access occurs after the start of the processor-initiated
access. If the HITM signal occurs one clock cycle before
the ADS = 0 of the processor-initiated access, the write-
back receives priority and is executed first.
However, if the snooping access is executed after the
start of the processor-initiated access, there is a
methodology to reorder the access order. The BOFF
signal delays outstanding processor-initiated cycles so
that a snoop write-back can occur immediately (see
Figure 13).
Note:
The circled numbers in this figure represent the steps in section 4.8.5.3.
CLK
ADR
M/IO
CACHE
W/R
ADS
BLAST
BRDY
AHOLD
INV
EADS
HITM
Data
BOFF
next clock cycle, the current address of the
write-back access is driven onto the address
bus.
and BRDY both transition to 0.
access, the snooping cache drives HITM back
to 1.
from CPU
1
2
Figure 12. Snoop Hit Cycle with Write-Back
3
to CPU
4
Am5
X
PRELIMINARY
86 Microprocessor
5
Read
Scenario : If there are outstanding processor-initiated
cycles on the bus, asserting BOFF clears the bus pipe-
line. If a snoop causes HITM to be asserted, the first
cycle issued by the microprocessor after deassertion of
BOFF is the write-back cycle. After the write-back cycle,
it reissues the aborted cycles. This translates into the
following sequence:
Step 1 The processor starts a cacheable burst read
Step 2 One clock cycle later, AHOLD is asserted. This
Step 3 Two clock cycles after AHOLD is asserted, the
Step 4 Two clock cycles after EADS is asserted, HITM
Step 5 Note that the processor-initiated access is not
Step 6 With HITM going Low, the core system logic
6
cycle.
switches the address bus into an input one clock
cycle after AHOLD is asserted.
EADS and INV signals are asserted to start the
snooping cycle.
becomes valid. The line is modified, therefore
HITM = 0.
completed because BLAST = 1.
asserts BOFF in the next clock cycle to the
snooping processor to reorder the access.
BOFF overrides BRDY. Therefore, the partial
read is not used. It is reread later.
7
W n
W n+4
W n+8
8
W n+C
from CPU
9
10
AMD
29