AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 33

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

4.9
The Am5
validation and flushing, much like the Am486 micropro-
cessor Write-through mode. However, the addition of
the write-back cache adds some complexity.
4.9.1 Cache Invalidation through Software
To invalidate the on-chip cache, the Am5
cessor family uses the same instructions as the Am486
microprocessor family. The two invalidation instruc-
tions, INVD and WBINVD, while similar, are slightly dif-
ferent for use in the write-back environment.
The WBINVD instruction first performs a write-back of
the modified data in the cache to external memory. Then
it invalidates the cache, followed by two special bus
cycles. The INVD instruction only invalidates the cache,
regardless of whether modified data exists, and follows
with a special bus cycle. The utmost care should be
taken when executing the INVD instruction to ensure
memory coherency. Otherwise, modified data may be
invalidated prior to writing back to main memory. In
Write-back mode, WBINVD requires a minimum of 4100
internal clocks to search the cache for modified data.
Writing back modified data adds to this minimum time.
WBINVD can only be stopped by a RESET.
Two special bus cycles follow the write-back of modified
data upon execution of the WBINVD instruction: first the
write-back, and then the flush special bus cycle. The
INVD operates identically to the standard 486 micropro-
cessor family in that the flush special bus cycle is gen-
HITM
ADS
BRDY
BLAST
CACHE
CLK
ADR
AHOLD
EADS
Cache Invalidation and Flushing in
Write-Back Mode
X
86 microprocessor family supports cache in-
n
Figure 15. Latest Snooping of Copy-Back
X
86 micropro-
Am5
X
PRELIMINARY
86 Microprocessor
S
erated when the on-chip cache is invalidated. Table 7
specifies the special bus cycle states for the instructions
WBINVD and INVD.
4.9.2 Cache Invalidation through Hardware
The other mechanism for cache invalidation is the
FLUSH pin. The FLUSH pin operates similarly to the
WBINVD command, writing back modified cache lines
to main memory. After the entire cache has copied back
all the modified data, the microprocessor generates two
special bus cycles. These special bus cycles signal to
the external caches that the microprocessor on-chip
cache has completed its copy-back and that the second
level cache may begin its copy-back to memory, if so
required.
Two flush acknowledge cycles are generated after the
FLUSH pin is asserted and the modified data in the
cache is written back. As with the WBINVD instruction,
in Write-back mode, a flush requires a minimum of 4100
internal clocks to test the cache for modified data. Writ-
ing back modified data adds to this minimum time. The
flush operation can only be stopped by a RESET. Table
8 shows the special flush bus cycle configuration.
A32–A2
0000 0000 h
0000 0000 h
Notes:
1. WBINVD generates first write-back, then flush.
2. INVD generates only flush.
Table 7. WBINVD/INVD Special Bus Cycles
M/IO D/C W/R BE3 BE2 BE1 BE0 Bus Cycle
0
0
0
0
1
1
0
1
1
1
Address B
1
0
1
1
Write-back
Flush
AMD
1, 2
33
1