AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 49

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

The recommended configuration is to use a separate
(non-overlaid) physical address for SMRAM. This non-
overlaid scheme prevents the CPU from improperly ac-
cessing the SMRAM or system RAM directly or through
the cache. Figure 33 shows the relative SMM timing for
non-overlaid SMRAM for systems configured in Write-
through mode. For systems configured in Write-back
mode, WB/WT must be driven Low (as shown in Figure
34) to force caching during SMM to be write-through.
Alternately, caching can be disabled during SMM by
deasserting KEN with SMI (as shown in Figure 35).
When the default SMRAM location is used, however,
SMRAM is overlaid with system main memory (at
38000h–3FFFFh). For simplicity, system designers may
want to use this default address, or they may select
another overlaid address range. However, in this case
the system control circuitry must use SMIACT to distin-
guish between SMRAM and main system memory, and
must restrict SMRAM space access to the CPU only.
To maintain cache coherency and to ensure proper
system operation in systems configured in Write-
through mode, the system must flush both the CPU inter-
nal cache and any second level caches in response to
SMIACT going Low. A system that uses cache during
SMM must flush the cache a second time in response
to SMIACT going High (see Figure 36). If KEN is driven
High when FLUSH is asserted, the cache is disabled
and a second flush is not required (see Figure 37). If the
system is configured in Write-back mode, the cache
must be flushed when SMI is asserted and then disabled
(see Figure 38).
7.8.2 Cache Flushes
The CPU does not unconditionally flush its cache before
entering SMM. Therefore, the designer must ensure
that, for systems using overlaid SMRAM, the cache is
flushed upon SMM entry and SMM exit if caching is
enabled.
Note: A cache flush in a system configured in Write-
back mode requires a minimum of 4100 internal clocks
to test the cache for modified data, whether invoked by
(no need to flush
Non-overlaid
SMRAM
memory
caches)
Normal
Figure 32. SMRAM Location
(caches must
be flushed)
Overlaid
memory
memory
Normal
Normal
Overlaid region
SMRAM
Am5
X
PRELIMINARY
86 Microprocessor
the FLUSH pin input or the WBINVD instruction, and
therefore invokes a performance penalty. There is no
flush penalty for systems configured in Write-through
mode.
If the flush at SMM entry is not done, the first SMM read
could hit in a cache that contains normal memory space
code/data instead of the required SMI handler, and the
handler could not be executed. If the cache is not dis-
abled and is not flushed at SMM exit, the normal read
cycles after SMM may hit in a cache that may contain
SMM code/data instead of the normal system memory
contents.
In Write-through mode, assert the FLUSH signal in re-
sponse to the assertion of SMIACT at SMM entry, and,
if required because the cache is enabled, assert FLUSH
again in response to the deassertion of SMIACT at SMM
exit (see Figure 36 and Figure 37). For systems config-
ured in Write-back mode, assert FLUSH with SMI (see
Figure 38).
Reloading the state registers at the end of SMM restores
cache functionality to its pre-SMM state.
7.8.3 A20M Pin
Systems based on the MS-DOS operating system con-
tain a feature that enables the CPU address bit A20 to
be forced to 0. This limits physical memory to a maxi-
mum of 1 Mbyte, and is provided to ensure compatibility
with those programs that relied on the physical address
wraparound functionality of the original IBM PC. The
A20M pin on Am5
When A20M is active, all external bus cycles drive A20
Low, and all internal cache accesses are performed with
A20 Low.
The A20M pin is recognized while the CPU is in SMM.
The functionality of the A20M input must be recognized
in two instances:
1. If the SMI handler needs to access system memory
2. If SMRAM has been relocated to address space
To account for these two situations, the system designer
must ensure that A20M is deasserted on entry to SMM.
A20M must be driven inactive before the first cycle of
the SMM state save, and must be returned to its original
level after the last cycle of the SMM state restore. This
can be done by blocking the assertion of A20M when
SMIACT is active.
space above 1 Mbyte (for example, when saving
memory to disk for a 0-V suspend), the A20M pin
must be deasserted before the memory above 1
Mbyte is addressed.
above 1 Mbyte, and A20M is active upon entering
SMM, the CPU attempts to access SMRAM at the
relocated address, but with A20 Low. This could
cause the system to crash, because there would be
no valid SMM interrupt handler at the accessed lo-
cation.
X
86 CPUs provides this function.
AMD
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