AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 19

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

hanced system support because the cache may contain
data that is not identical to data in main memory at the
same address location.
4.5
The Am5
coherency protocol reduces bus activity while maintain-
ing data coherency in a multimaster environment. The
cache coherency protocol offers the following advan-
tages:
The Am5
ified MESI protocol on systems with write-back cache
support. MESI allows a cache line to exist in four states:
modified, exclusive, shared, and invalid. The Am5
microprocessor family allocates memory in the cache
due to a read miss. Write allocation is not implemented.
To maintain coherency between cache and main mem-
ory, the MESI protocol has the following characteristics:
4.5.1 Cache Line Overview
To implement the Am5
herency protocol, each tag entry is expanded to 2 bits:
S1 and S0. Each tag entry is associated with a cache
line. Table 3 shows the cache line organization.
Data Words (32 Bits)
No unnecessary bus traffic. The protocol dynamical-
ly identifies shared data to the granularity of a cache
line. This dynamic identification ensures that the traf-
fic on the external bus is the minimum necessary to
ensure coherency.
Software-transparent. Because the protocol gives
the appearance of a single, unified memory, soft-
ware does not have to maintain coherency or identify
shared data. Application software developed for a
system without a cache can run without modification.
Software support is required only in the operating
system to identify non-cacheable data regions.
The system memory is always updated during a
snoop when a modified line is hit.
If a modified line is hit by another master during
snooping, the master is forced off the bus and the
snooped cache writes back the modified line to the
system memory. After the snooped cache completes
the write, the forced-off bus master restarts the ac-
cess and reads the modified data from memory.
Write-Back Cache Protocol
X
Table 3. Cache Line Organization
X
86 microprocessor family implements a mod-
86 microprocessor family write-back cache
D0
D1
D2
D3
X
86 microprocessor cache co-
Address Tag and Status
Address Tag, S1, S0
Am5
X
PRELIMINARY
86 Microprocessor
X
86
4.5.2 Line Status and Line State
A cache line can occupy one of four legal states as
indicated by bits S0 and S1. The line states are shown
in Table 4. Each line in the cache is in one of these
states. The state transition is induced either by the pro-
cessor or during snooping from an external bus master.
4.5.2.1
An invalid cache line does not contain valid data for any
external memory location. An invalid line does not par-
ticipate in the cache coherency protocol.
4.5.2.2
An exclusive line contains valid data for some external
memory location. The data exactly matches the data in
the external memory location.
4.5.2.3
A shared line contains valid data for an external memory
location, the data is shared by another cache, and the
shared data matches the data in the external memory
exactly; or the cache line is in Write-through mode.
4.5.2.4
A modified line contains valid data for an external mem-
ory location. However, the data does not match the data
in the external location because the processor has mod-
ified the data since it was loaded from the external mem-
ory. A cache that contains a modified line is responsible
for ensuring that the data is properly maintained. This
means that in the case of an external access to that line
from another external bus master, the modified line is
first written back to the external memory before the other
external bus master can complete its access. Table 5
shows the MESI cache line states and the correspond-
ing availability of data.
S1
0
0
1
1
Table 4. Legal Cache Line States
Invalid
Exclusive
Shared
Modified
S0
0
1
0
1
Line State
Exclusive
Modified
Shared
Invalid
AMD
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