AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 37

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

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5.4
Table 9 shows the pin states during Stop Grant Bus
states. During the Stop Grant state, most output and
input/output signals of the microprocessor maintain the
level they held when entering the Stop Grant state. The
data and data parity signals are tri-stated. In response
to HOLD being driven active during the Stop Grant state
(when the CLK input is running), the CPU generates
HLDA and tri-states all output and input/output signals
that are tri-stated during the HOLD/HLDA state. After
HOLD is deasserted, all signals return to the same state
they were before the HOLD/HLDA sequence.
CLK
STPCLK
A3–A2
A31–A4
D31–D0
BE3–BE0
DP3–DP0
W/R, D/C, M/IO, CACHE
ADS
LOCK, PLOCK
BREQ
HLDA
BLAST
FERR
PCHK
SMIACT
HITM
ADDR
RDY
Table 9. Pin State During Stop Grant Bus State
Pin State During Stop Grant
Signal
t
20
Type
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
t
21
Previous State
Previous State
Floated
Previous State
Floated
Previous State
Inactive
Inactive
Previous State
As per HOLD
Previous State
Previous State
Previous State
Previous State
Previous State
Figure 19. Entering Stop Grant State
State
Am5
X
PRELIMINARY
86 Microprocessor
To achieve the lowest possible power consumption dur-
ing the Stop Grant state, the system designer must en-
sure that the input signals with pull-up resistors are not
driven Low, and the input signals with pull-down resis-
tors are not driven High.
All inputs except data bus pins must be driven to the
power supply rails to ensure the lowest possible current
consumption during Stop Grant or Stop Clock modes.
For compatibility, data pins must be driven Low to
achieve the lowest possible power consumption.
5.5
Figure 20 shows the state transitions during a Stop
Clock cycle.
5.5.1 Normal State
This is the normal operating state of the CPU. While in
the normal state, the CLK input can be dynamically
changed within the specified CLK period stability limits.
5.5.2 Stop Grant State
The Stop Grant state provides a low-power state that
can be entered by simply asserting the external STPCLK
interrupt pin. When the Stop Grant bus cycle has been
placed on the bus, and either RDY or BRDY is returned,
the CPU is in this state. The CPU returns to the normal
execution state 10–20 clock cycles after STPCLK has
been deasserted.
While in the Stop Grant state, the pull-up resistors on
STPCLK and UP are disabled internally. The system
must continue to drive these inputs to the state they
were in immediately before the CPU entered the Stop
Grant State. For minimum CPU power consumption, all
other input pins should be driven to their inactive level
while the CPU is in the Stop Grant state.
Clock Control State Diagram
Stop Grant Bus cycle
AMD
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