AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 34

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

34
4.9.3 Snooping During Cache Flushing
As with snooping during normal operation, snooping is
permitted during a cache flush, whether initiated by the
FLUSH pin or WBINVD instruction. After completion of
the snoop, and write-back, if needed, the microproces-
sor completes the copy-back of modified cache lines.
4.10 Burst Write
The Am5
mance by implementing a burst write feature for cache
A32–A2
0000 0001h
0000 0001h
CLK
ADR
M/IO
W/R
CACHE
ADS
BLAST
BRDY
BOFF
Data
to CPU
AMD
Table 8. FLUSH Special Bus Cycles
X
86 microprocessor improves system perfor-
M/IO D/C W/R BE3 BE2 BE1 BE0 Bus Cycle
CLK
ADR
M/IO
W/R
CACHE
ADS
BLAST
BRDY
Data
0
0
0
0
1
1
XX0
XX0
0
1
1
1
Figure 17. Burst Read with BOFF Assertion
XX4
XX4
1
0
XX0
1
1
XX0
First Flush
Acknowledge
Second
Flush
Acknowledge
Am5
Figure 16. Burst Write
X
PRELIMINARY
86 Microprocessor
XX4
XX4
line write-backs and copy-backs. Standard write oper-
ations are still supported. Burst writes are always four
32-bit words and start at the beginning of a cache line
address of 0 for the starting access. The timing of the
BLAST and BRDY signals is identical to the burst read.
Figure 16 shows a burst write access. (See Figure 17
and Figure 18 for burst read and burst write access with
BOFF asserted.) In addition to using BLAST, the
CACHE signal indicates burstable cycles.
CACHE is a cycle definition pin used when in Write-back
mode (CACHE floats in Write-through mode). For pro-
cessor-initiated cycles, the signal indicates:
don’t care
For a read cycle, the internal cacheability of the cycle
For a write cycle, a burst write-back or copy-back, if
KEN is asserted (for linefills).
XX8
XX8
XX4
XX4
XXC
XXC
XX8
XX8
XXC
XXC