AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 39

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

The Am5
held active until the CPU issues an interrupt acknowl-
edge cycle to guarantee recognition. This condition also
applies to the existing Am486 CPUs.
In the Stop Grant state, the system can stop or change
the CLK input. When the clock stops, the CPU enters
the Stop Clock state. The CPU returns to the Stop Grant
state immediately when the CLK input is restarted. You
must hold the STPCLK input Low until a stabilized fre-
quency has been maintained for at least 1 ms to ensure
that the PLL has had sufficient time to stabilize.
The CPU generates a Stop Grant bus cycle when en-
tering the state from the Normal or the Auto HALT Power
Down state. When the CPU enters the Stop Grant state
from the Stop Clock state or the Stop Clock Snoop state,
the CPU does not generate a Stop Grant bus cycle.
5.5.3 Stop Clock State
Stop Clock state is entered from the Stop Grant state
by stopping the CLK input (either logic High or logic
Low). None of the CPU input signals should change
state while the CLK input is stopped. Any transition on
an input signal (except INTR) before the CPU has re-
turned to the Stop Grant state may result in unpredict-
able behavior. If INTR goes active while the CLK input
is stopped, and stays active until the CPU issues an
interrupt acknowledge bus cycle, it is serviced in the
normal manner. System design must ensure the CPU
is in the correct state prior to asserting cache invalidation
or interrupt signals to the CPU.
5.5.4 Auto Halt Power Down State
A HALT instruction causes the CPU to enter the Auto
HALT Power Down state. The CPU issues a normal
HALT bus cycle, and only transitions to the Normal state
when INTR, NMI, SMI, RESET, or SRESET occurs.
The system can generate a STPCLK while the CPU is
in the Auto HALT Power Down state. The CPU gener-
ates a Stop Grant bus cycle when it enters the Stop
Grant state from the HALT state. When the system deas-
serts the STPCLK interrupt, the CPU returns execution
to the HALT state. The CPU generates a new HALT bus
cycle when it reenters the HALT state from the Stop
Grant state.
5.5.5 Stop Clock Snoop State
When the CPU is in the Stop Grant state or the Auto
HALT Power Down state, the CPU recognizes HOLD,
AHOLD, BOFF, and EADS for cache invalidation. When
the system asserts HOLD, AHOLD, or BOFF, the CPU
floats the bus accordingly. When the system asserts
EADS, the CPU transparently enters Stop Clock Snoop
state and powers up for one full clock to perform the
required cache snoop cycle. If a modified line is
snooped, a cache write-back occurs with HITM transi-
(Cache Invalidations)
X
86 CPU product family requires INTR to be
Am5
X
PRELIMINARY
86 Microprocessor
tioning active until the completion of the write-back. It
then powers down and returns to the previous state. The
CPU does not generate a bus cycle when it returns to
the previous state.
5.5.6 Cache Flush State
When configured in Write-back mode, the processor
recognizes FLUSH for copying back modified cache
lines to memory in the Auto Halt Power Down State or
Normal State. Upon the completion of the cache flush,
the processor returns to its prior state, and regenerates
a special bus cycle, if necessary.
6
The Am5
set function through the SRESET pin. SRESET forces
the processor to begin execution in a known state. The
processor state after SRESET is the same as after RE-
SET except that the internal caches, CD and NW in CR0,
write buffers, SMBASE registers, and floating-point reg-
isters retain the values they had prior to SRESET, and
cache snooping is allowed. The processor starts exe-
cution at physical address FFFFFFF0h. SRESET can
be used to help performance for DOS extenders written
for the 80286 processor. SRESET provides a method
to switch from Protected to Real mode while maintaining
the internal caches, CR0, and the FPU state. SRESET
may not be used in place of RESET after power-up.
In Write-back mode, once SRESET is sampled active,
the SRESET sequence begins on the next instruction
boundary (unless FLUSH or RESET occur before that
boundary). When started, the SRESET sequence con-
tinues to completion and then normal processor execu-
tion resumes, independent of the deassertion of
SRESET. If a snoop hits a modified line during SRESET,
a normal write-back cycle occurs. ADS is asserted to
drive the bus cycles even if SRESET is not deasserted.
7
7.1
The Am5
al, Virtual, Protected, and System Management mode
(SMM). As an operating mode, SMM has a distinct pro-
cessor environment, interface, and hardware/software
features. SMM lets the system designer add new soft-
ware-controlled features to the computer products that
always operate transparent to the operating system
(OS) and software applications. SMM is intended for
use only by system firmware, not by applications soft-
ware or general purpose systems software.
The SMM architectural extension consists of the follow-
ing elements:
System Management Interrupt (SMI) hardware in-
terface
SRESET FUNCTION
SYSTEM MANAGEMENT MODE
Overview
X
X
86 microprocessor supports four modes: Re-
86 microprocessor family supports a soft re-
AMD
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