AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 38

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

38
A RESET or SRESET brings the CPU from the Stop
Grant state to the Normal state. The CPU recognizes
the inputs required for cache invalidations (HOLD,
AHOLD, BOFF, and EADS) as explained later. The CPU
does not recognize any other inputs while in the Stop
Grant state. Input signals to the CPU are not recognized
until 1 clock after STPCLK is deasserted (see Figure 21).
Note: A = Earliest time at which NMI or SMI is recognized.
STPCLK
AMD
CLK
NMI
SMI
(valid for Write-back mode only)
Figure 21. Recognition of Inputs when Exiting Stop Grant State
STPCLK
Sampled
t
20
Figure 20. Stop Clock State Machine
t
Am5
21
X
PRELIMINARY
86 Microprocessor
A
While in the Stop Grant state, the CPU does not recog-
nize transitions on the interrupt signals (SMI, NMI, and
INTR). Driving an active edge on either SMI or NMI does
not guarantee recognition and service of the interrupt
request following exit from the Stop Grant state. How-
ever, if one of the interrupt signals (SMI, NMI, or INTR)
is driven active while the CPU is in the Stop Grant state,
and held active for at least one CLK after STPCLK is
deasserted, the corresponding interrupt will be serviced.