SAA7109 PHILIPS [NXP Semiconductors], SAA7109 Datasheet - Page 21

• Manufacturer Part Number: SAA7109
• Description: PC-CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
8.8
The FIFO acts as a buffer to translate from the PIXCLK
clock domain to the XTAL clock domain. The write clock is
PIXCLK and the read clock is XTAL. An underflow or
overflow condition can be detected via the I
access.
In order to avoid underflows and overflows, it is essential
that the frequency of the synthesized PIXCLK matches to
the input graphics resolution and the desired scaling
factor. It is suggested to refer to Tables 6 to 23 for some
representative combinations.
8.9
When the graphics picture is to be displayed as interlaced
PAL, NTSC, S-video or RGB on a TV screen, it is desired
in many cases not to lose picture information due to the
inherent overscanning of a TV set. The desired amount of
underscan area, which is achieved through appropriate
scaling in the vertical and horizontal direction, can be filled
in the border generator with an arbitrary true colour tint.
8.10
The master clock generation is realized as a 27 MHz
crystal oscillator, which can operate with either a
fundamental wave crystal or a 3rd-harmonic crystal.
The crystal clock supplies the DTO of the pixel clock
synthesizer, the video encoder and the I
block. It also usually supplies the triple DAC, with the
exception of the auxiliary VGA mode, where the triple DAC
is clocked by the pixel clock (PIXCLK).
The DTO can be programmed to synthesize all relevant
pixel clock frequencies between circa 18 and 44 MHz.
8.11
This block reduces the phase jitter of the synthesized pixel
clock. It works as a tracking filter for all relevant
synthesized pixel clock frequencies.
8.12
8.12.1
The encoder generates luminance and colour subcarrier
output signals from the Y, C
which are suitable for use as CVBS or separate Y and C
signals.
2004 Mar 16
PC-CODEC
FIFO
Border generator
Oscillator and Discrete Time Oscillator (DTO)
Low-pass Clock Generation Circuit (CGC)
Encoder
V
IDEO PATH
B
and C
R
baseband signals,
2
C-bus control
2
C-bus read
21
Input to the encoder, at 27 MHz clock (e.g. DVD), is either
originated from computer graphics at pixel clock, fed
through the FIFO and border generator, or a ITU-R BT.656
style signal.
Luminance is modified in gain and in offset (the offset is
programmable in a certain range to enable different black
level set-ups). A blanking level can be set after insertion of
a fixed synchronization pulse tip level, in accordance with
standard composite synchronization schemes. Other
manipulations used for the Macrovision anti-taping
process, such as additional insertion of AGC super-white
pulses (programmable in height), are supported by the
SAA7108E only.
To enable easy analog post filtering, luminance is
interpolated from a 13.5 MHz data rate to a 27 MHz data
rate, thereby providing luminance in a 10-bit resolution.
The transfer characteristics of the luminance interpolation
filter are illustrated in Figs 7 and 8. Appropriate transients
at start/end of active video and for synchronization pulses
are ensured.
Chrominance is modified in gain (programmable
separately for C
burst is inserted, before baseband colour signals are
interpolated from a 6.75 MHz data rate to a 27 MHz data
rate. One of the interpolation stages can be bypassed,
thus providing a higher colour bandwidth, which can be
used for the Y and C output. The transfer characteristics of
the chrominance interpolation filter are illustrated in
Figs 5 and 6.
The amplitude (beginning and ending) of the inserted
burst, is programmable in a certain range that is suitable
for standard signals and for special effects. After the
succeeding quadrature modulator, colour is provided on
the subcarrier in 10-bit resolution.
The numeric ratio between the Y and C outputs is in
accordance with the standards.
8.12.2
Pin TTX_SRES receives a WST or NABTS teletext
bitstream sampled at the crystal clock. At each rising edge
of the output signal (TTXRQ) a single teletext bit has to be
provided after a programmable delay at input pin
TTX_SRES.
T
SIMULTANEOUSLY WITH REAL
ELETEXT INSERTION AND ENCODING
B
and C
SAA7108E; SAA7109E
R
), and a standard dependent
-
TIME CONTROL
Product specification
(
NOT
)