SAA7109 PHILIPS [NXP Semiconductors], SAA7109 Datasheet - Page 83

• Manufacturer Part Number: SAA7109
• Description: PC-CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 43 Vertical phase offset usage; assignment of the phase offsets
Notes
1. Case 1: OFIDC[90H[6]] = 0; scaler input field ID as output ID; back-end interprets output field ID at logic 0 as upper
2. Case 2: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 0 as upper output
3. Case 3: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 1 as upper output
9.4
The SAA7108E; SAA7109E contains a versatile VBI data
decoder.
The implementation and programming model accords to
the VBI data slicer the built-in multimedia video data
acquisition circuit of the SAA5284.
The circuitry recovers the actual clock phase during the
clock run-in period, slices the data bits with the selected
data rate, and groups them into bytes. The result is
buffered into a dedicated VBI data FIFO with a capacity of
2
source, field frequency and accepted error count must be
defined in subaddress 40H.
The VBI data standards that are supported are given in
Table 44.
2004 Mar 16
0 = upper lines
0 = upper lines
1 = lower lines
1 = lower lines
PC-CODEC
DETECTED INPUT
56 bytes (2
output lines.
lines.
lines.
VBI data decoder and capture
(subaddresses 40H to 7FH)
FIELD ID
14 Dwords). The clock frequency, signal
0
1
0
1
TASK STATUS BIT
YPY0[7:0] and
YPC0[7:0]
YPY1[7:0] and
YPC1[7:0]
YPY2[7:0] and
YPC2[7:0]
YPY3[7:0] and
YPC3[7:0]
VERTICAL PHASE
OFFSET
83
For lines 2 to 24 of a field, per VBI line, 1 of 16 standards
can be selected (LCRxxx[41:57[7:0]]: 23
programming bits). The definition for line 24 is valid for the
rest of the corresponding field, normally no text data (video
data) should be selected there (LCR24 = FFH) to stop the
activity of the VBI data slicer during active video.
To adjust the slicers processing to the input signal source,
there are offsets in the horizontal and vertical direction
available (parameters HOFF[5B,59[2:0,7:0]],
VOFF[5B,5A[4,7:0]] and FOFF[5B[7]]).
In difference to the scalers counting, the slicers offsets
define the position of the horizontal and vertical trigger
events related to the processed video field. The trigger
events are the falling edge of HREF and the falling edge of
V123 from the decoder processing part.
The relationship of these programming values to the input
signal and the recommended values can be seen in
Tables 34 to 37.
case 1
case 2
case 3
case 1
case 2
case 3
case 1
case 2
case 3
case 1
case 2
case 3
CASE
(1)
(2)
(3)
SAA7108E; SAA7109E
UP-UP (PHO)
UP-UP
UP-LO
UP-UP (PHO)
UP-LO
UP-UP
LO-LO
LO-UP
LO-LO
LO-LO
LO-LO
LO-UP
EQUATION TO BE USED
PHO
PHO
+
+
Product specification
YSCY[15:0]
------------------------------ - 16
YSCY[15:0]
------------------------------ - 16
2
64
64
4-bit
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