SAA7109 PHILIPS [NXP Semiconductors], SAA7109 Datasheet - Page 97

• Manufacturer Part Number: SAA7109
• Description: PC-CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
10.4.2
If data input mode is selected at the expansion port, then
the scaler can choose its input data stream from the
on-chip video decoder, or from the expansion port
(controlled by bit SCSRC[1:0] 91H[5:4]). Byte serial
Y-C
or raw samples from an external ADC may be input (see
also bits FSC[2:0] 91H[2:0]). The input data stream must
be accompanied by an external clock XCLK, qualifier XDQ
and reference signals XRH and XRV. Instead of the
reference signal, embedded SAV and EAV codes,
according to ITU 656, can also be accepted. The
protection bits are not evaluated.
XRH and XRV carry the horizontal and vertical
synchronization signals for the digital video stream
through the expansion port. The field ID of the input video
stream is carried in the phase (edge) of XRV and state of
XRH, or directly as FS (frame sync, odd/even signal) on
the XRV pin (controlled by XFDV[92H[7]], XFDH[92H[6]]
and XDV[1:0] 92H[5:4]).
The trigger events on XRH (rising/falling edge) and XRV
(rising/falling both edges) for the scalers acquisition
window are defined by XDV[1:0] 92H[5:4] and
XDH[92H[2]]. The signal polarity of the qualifier can also
be defined by bit XDQ[92H[1]]. As an alternative to the
qualifier, the input clock can be applied to a gated clock
(clock gated with a data qualifier, controlled by bit
XCKS[92H[0]]). In this event, all input data will be qualified.
10.5
The image port transfers data from the scaler as well as
from the VBI data slicer, if selected (maximum 33 MHz).
The reference clock is available at the ICLK pin as an
output or as an input (maximum 33 MHz). As an output,
the ICLK is derived from the line-locked decoder or
expansion port input clock. The data stream from the
scaler output is normally discontinuous. Therefore valid
data during a clock cycle is accompanied by a data
qualifying (data valid) flag on pin IDQ. For pin constrained
applications the IDQ pin can be programmed to function as
a gated clock output (bit ICKS2[80H[2]]).
2004 Mar 16
PC-CODEC
B
-C
Image port (I port)
R
X
4 : 2 : 2, or subsets for other sampling schemes,
PORT CONFIGURED AS INPUT
97
The data formats at the image port are defined in Dwords
of 32 bits (4 bytes), such as the related FIFO structures.
However, the physical data stream at the image port is
only 16-bit or 8-bit wide; in 16-bit mode data pins HPD7
to HPD0 are used for chrominance data. The four bytes of
the Dwords are serialized in words or bytes.
The available formats are as follows:
For handshaking with the receiving VGA controller, or
other memory or bus interface circuitry, F, H and V
reference signals and programmable FIFO flags are
provided. The information is provided on pins IGP0, IGP1,
IGPH and IGPV. The function on these pins is controlled
via subaddresses 84H and 85H.
VBI data is collected over an entire line in its own FIFO and
transferred as an uninterrupted block of bytes. Decoded
VBI data can be signed by the VBI flag on pins IGP0 and
IGP1.
Because scaled video data and decoded VBI data may
come from different and asynchronous sources, an
arbitration scheme is needed. Normally the VBI data slicer
has priority.
The image port consists of the pins and/or signals, as
given in Table 62.
For pin constrained applications, or interfaces, the relevant
timing and data reference signals can also be encoded into
the data stream. Therefore the corresponding pins do not
need to be connected. The minimum image port
configuration requires 9 pins only, i.e. 8 pins for data
including codes, and 1 pin for clock or gated clock. The
inserted codes are defined in close relationship to the
ITU-R BT.656 (D1) recommendation, where possible.
Y-C
Y-C
Raw samples
Decoded VBI data.
B
B
-C
-C
R
R
4 : 2 : 2
4 : 1 : 1
SAA7108E; SAA7109E
Product specification