SAA7109 PHILIPS [NXP Semiconductors], SAA7109 Datasheet - Page 84

• Manufacturer Part Number: SAA7109
• Description: PC-CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 44 Data types supported by the data slicer block
9.5
The output interface consists of a FIFO for video and for
sliced text data, an arbitration circuit, which controls the
mixed transfer of video and sliced text data over the I port,
and a decoding and multiplexing unit, which generates the
8 or 16-bit wide output data stream together with the
accompanying reference and help information.
The clock for the output interface can be derived from an
internal clock, decoder, expansion port or an externally
provided clock which is appropriate, for example, for the
VGA and frame buffer. The clock can be up to 33 MHz.
The scaler provides the following video related timing
reference events (signals), which are available on pins as
defined by subaddresses 84H and 85H:
2004 Mar 16
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DATA TYPE
Output field ID
Start and end of vertical active video range
Start and end of active video line
Data qualifier or gated clock
Actually activated programming page (if CONLH is
used)
Threshold controlled FIFO filling flags (empty, full, filled)
Sliced data marker.
PC-CODEC
NUMBER
Image port output formatter
(subaddresses 84H to 87H)
teletext EuroWST, CCST
European Closed Caption
VPS
wide screen signalling bits
US teletext (WST)
US Closed Caption (line 21)
(video data selected)
(raw data selected)
teletext
VITC/EBU time codes (Europe)
VITC/SMPTE time codes (USA)
US NABTS
MOJI (Japanese)
Japanese format switch (L20/22) 5
no sliced data transmitted
(video data selected)
STANDARD TYPE
6.9375
0.500
5
5
5.7272
0.503
5
5
6.9375
1.8125
1.7898
5
5.7272
5.7272
5
DATA RATE
(Mbits/s)
84
The disconnected data stream at the scaler output is
accompanied by a data valid flag (or data qualifier), or is
transported via a gated clock. Clock cycles with invalid
data on the I port data bus (including the HPD pins in 16-bit
output mode) are marked with code 00H.
The output interface also arbitrates the transfer between
scaled video data and sliced text data over the I port
output.
The bits VITX1 and VITX0 (subaddress 86H) are used to
control the arbitration.
The serialization of the internal 32-bit Dwords to 8-bit or
16-bit output (optional), as well as the insertion of the
extended ITU 656 codes (SAV/EAV for video data, ANC or
SAV/EAV codes for sliced text data) are also done here.
For handshaking with the VGA controller, or other memory
or bus interface circuitry, programmable FIFO flags are
provided; see Section 9.5.2.
27H
001
9951H
1E3C1FH
27H
001
none
none
programmable
programmable
programmable
programmable
programmable
programmable (A7H) Japtext
programmable
none
FRAMING CODE
SAA7108E; SAA7109E
WST625
CC625
VPS
WSS
WST525
CC525
disable
disable
general text
VITC625
VITC525
open
NABTS
open
disable
WINDOW
FC
Product specification
always
always
optional
optional
CHECK
HAM