SAA7109 PHILIPS [NXP Semiconductors], SAA7109 Datasheet - Page 92

• Manufacturer Part Number: SAA7109
• Description: PC-CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
10 INPUT/OUTPUT INTERFACES AND PORTS OF
The SAA7108E; SAA7109E has 5 different I/O interfaces.
These are:
Table 54 Analog pin description
10.2
The SAA7108E; SAA7109E also synchronizes the audio clock and sampling rate to the video frame rate, via a very slow
PLL. This ensures that the multimedia capture and compression processes always gather the same predefined number
of samples per video frame.
An audio master clock AMCLK and two divided clocks, ASCLK and ALRCLK, are generated; see Table 55.
The ratios are programmable, see Section 9.6.
Table 55 Audio clock pin description
2004 Mar 16
AI24 to AI21
AI12 and AI11
AOUT
AI1D and AI2D P12 and P8
SYMBOL
AMCLK
AMXCLK J12
ASCLK
ALRCLK
Analog video input interface, for analog CVBS and/or
Y and C input signals
Audio clock port
Digital real-time signal port (RT port)
Digital video expansion port (X port), for unscaled digital
video input and output
Digital image port (I port) for scaled video data output
and programming
Digital host port (H port) for extension of the image port
or expansion port from 8 to 16-bit.
ALRCLK: audio left/right channel clock.
PC-CODEC
ASCLK: can be used as audio serial clock
SYMBOL
DIGITAL VIDEO DECODER PART
Audio clock signals
K12
K14
J13
PIN
P6, P7, P9
and P10
P11 and P13
M10
O
I
O
O
I/O
PIN
audio master clock output
external audio master clock input for the clock
division circuit, can be directly connected to
output AMCLK for standard applications
serial audio clock output, can be synchronized to
rising or falling edge of AMXCLK
audio channel (left/right) clock output, can be
synchronized to rising or falling edge of ASCLK
I
O
I
I/O
analog video signal inputs, e.g. 2 CVBS signals and
two Y/C pairs can be connected simultaneously
analog video output, for test purposes
analog reference pins for differential ADC operation
DESCRIPTION
92
DESCRIPTION
10.1
The SAA7108E; SAA7109E has 6 analog inputs
AI21 to AI24, AI11 and AI12 (see Table 54) for composite
video CVBS or S-video Y/C signal pairs. Additionally, there
are two differential reference inputs, which must be
connected to ground via a capacitor equivalent to the
decoupling capacitors at the 6 inputs. There are no
peripheral components required other than the decoupling
capacitors and 18 /56
per connected input signal (see also application example
in Fig.52). Two anti-alias filters are integrated, and self
adjusting via the clock frequency.
Clamp and gain control for the two ADCs are also
integrated. An analog video output pin (AOUT) is provided
for testing purposes.
Analog terminals
ACPF[17:0] 32H[1:0] 31H[7:0] 30H[7:0]
and ACNI[21:0] 36H[5:0] 35H[7:0]
34H[7:0]
SDIV[5:0] 38H[5:0] and SCPH[3AH[0]]
LRDIV[5:0] 39H[5:0] and LRPH[3AH[1]]
SAA7108E; SAA7109E
termination resistors, one set
BIT
MODE3 to MODE0
AOSL1 and AOSL0
Product specification
BIT