ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 107

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

Table 113. Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, Address 0x88)
Bit
7
6
5
4
3
2
1
0
1
Table 114. Timer/Counter 2 Control SFR (T2CON, Address 0xC8)
Bit
7
6
5
4
3
2
1
0
These bits are not used to control Timer/Counter 0 and Timer/Counter 1 but are instead used to control and monitor the external INT0 and INT1 interrupt pins.
Bit Address
0x8F
0x8E
0x8D
0x8C
0x8B
0x8A
0x89
0x88
Bit Address
0xCF
0xCE
0xCD
0xCC
0xCB
0xCA
0xC9
0xC8
Mnemonic
Mnemonic
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CAP2
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
1
1
1
1
Default
0
0
0
0
0
0
0
0
Default
0
0
0
0
0
0
0
0
Description
Timer 1 overflow flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware
when the program counter (PC) vectors to the interrupt service routine.
Timer 1 run control bit. Set by the user to turn on Timer/Counter 1. Cleared by the user to turn
off Timer/Counter 1.
Timer 0 overflow flag. Set by hardware on a Timer/Counter 0 overflow. Cleared by hardware
when the PC vectors to the interrupt service routine.
Timer 0 run control bit. Set by the user to turn on Timer/Counter 0. Cleared by the user to turn
off Timer/Counter 0.
External Interrupt 1 (INT1) flag. Set by hardware by a falling edge or by a zero level applied to
the external interrupt pin, INT1, depending on the state of Bit IT1. Cleared by hardware when
the PC vectors to the interrupt service routine only if the interrupt was transition activated. If level
activated, the external requesting source, rather than the on-chip hardware, controls the
request flag.
External Interrupt 1 (IE1) trigger type. Set by software to specify edge sensitive detection, that is,
a 1-to-0 transition. Cleared by software to specify level sensitive detection, that is, zero level.
External Interrupt 0 (INT0) flag. Set by hardware by a falling edge or by a zero level being
applied to the external interrupt pin, INT0, depending on the state of Bit IT0. Cleared by
hardware when the PC vectors to the interrupt service routine only if the interrupt was
transition activated. If level activated, the external requesting source, rather than the on-chip
hardware, controls the request flag.
External Interrupt 0 (IE0) trigger type. Set by software to specify edge sensitive detection, that is,
1-to-0 transition. Cleared by software to specify level sensitive detection, that is, zero level.
Description
Timer 2 overflow flag. Set by hardware on a Timer 2 overflow. TF2 cannot be set when either
RCLK = 1 or TCLK = 1. Cleared by user software.
Timer 2 external flag. Set by hardware when either a capture or reload is caused by a negative
transition on the T2EX pin and EXEN2 = 1. Cleared by user software.
Receive clock enable bit. Set by the user to enable the serial port to use Timer 2 overflow pulses
for its receive clock in Serial Port Mode 1 and Serial Port Mode 3. Cleared by the user to enable
Timer 1 overflow to be used for the receive clock.
Transmit clock enable bit. Set by the user to enable the serial port to use Timer 2 overflow pulses
for its transmit clock in Serial Port Mode 1 and Serial Port Mode 3. Cleared by the user to enable
Timer 1 overflow to be used for the transmit clock.
Timer 2 external enable flag. Set by the user to enable a capture or reload to occur as a result of
a negative transition on the T2EX pin if Timer 2 is not being used to clock the serial port. Cleared
by the user for Timer 2 to ignore events at T2EX.
Timer 2 start/stop control bit. Set by the user to start Timer 2. Cleared by the user to stop Timer 2.
Timer 2 timer or counter function select bit. Set by the user to select the counter function (input
from the external T2 pin). Cleared by the user to select the timer function (input from the on-chip core
clock).
Timer 2 capture/reload select bit. Set by the user to enable captures on negative transitions at
the T2EX pin if EXEN2 = 1. Cleared by the user to enable autoreloads with Timer 2 overflows or
negative transitions at the T2EX pin when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is
ignored and the timer is forced to autoreload on Timer 2 overflow.
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