ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 27

no-image

ADE5166_08

Manufacturer Part Number
ADE5166_08
Description
Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
Manufacturer
AD [Analog Devices]
Datasheet
POWER SUPPLY ARCHITECTURE
The ADE5166/ADE5169 have two power supply inputs, V
V
full operation. A battery backup, or secondary power supply, with
a maximum of 3.7 V can be connected to the V
the ADE5166/ADE5169 connect V
used to derive power for the ADE5166/ADE5169 circuitry. The
V
(V
can also be used to power a limited number of peripheral compo-
nents. The 2.5 V analog supply (V
the core logic (V
V
architecture.
The ADE5166/ADE5169 provide automatic battery switchover
between V
or V
battery switchover. The conditions for switching V
to V
section. V
3.3 V dc signal. This input is intended for power supply super-
visory purposes and does not provide power to the ADE5166/
ADE5169 circuitry (see the Battery Switchover section).
BATTERY SWITCHOVER
The ADE5166/ADE5169 monitor V
matic battery switchover from V
based on the status of the V
switchover is enabled by default. Setting Bit 1 in the battery
switchover configuration SFR (BATPR, Address 0xF5) disables
battery switchover so that V
Table 18). The source of V
peripheral configuration SFR (PERIPH, Address 0xF4), which is
described in Table 19. Bit 6 is set when V
V
The battery switchover functionality provided by the ADE5166/
ADE5169 allows a seamless transition from V
matic battery switchover option ensures a stable power supply to
the ADE5166/ADE5169, as long as the external battery voltage
BAT
SWOUT
SWOUT
DD
BCTRL
SWOUT
, and they require only a single 3.3 V power supply at V
BAT
DCIN
and cleared when V
. Figure 30 shows the ADE5166/ADE5169 power supply
output pin reflects the voltage at the internal power supply
and back to V
) and has a maximum output current of 6 mA. This pin
. In addition, the BCTRL input can be used to trigger a
V
DCIN
DCIN
DD
POWER SUPPLY
MANAGEMENT
SCRATCH PAD
and V
is an input pin that can be connected to a 0 V to
V
DD
INTD
Figure 30. Power Supply Architecture
TEMPERATURE ADC
BAT
V
) are derived by on-chip linear regulators from
BAT
DD
based on the voltage level detected at V
are described in the Battery Switchover
SWOUT
V
ADC
SW
DD
SWOUT
DD
, the V
ADC
LCD
V
is always connected to V
is connected to V
SWOUT
is indicated by Bit 6 in the
INTA
DD
DD
DCIN
to V
) and the 2.5 V supply for
or V
DD
LDO
LDO
RTC
, or the BCTRL pin. Battery
, V
BAT
BAT
SWOUT
BAT
can be configured
to V
V
V
, and V
3.3V
DD
INTD
INTA
BAT
to V
is connected to
SWOUT
BAT
SWOUT
input. Internally,
.
BAT
DCIN
2.5V
SPI/I
UART
, which is
MCU
ADE
SWOUT
. An auto-
from V
. Auto-
2
C
DD
DD
(see
and
Rev. 0 | Page 27 of 148
for
DD
DD
is above 2.75 V. It allows continuous code execution even while
the internal power supply is switching from V
Note that the energy metering ADCs are not available when
V
Power supply management (PSM) interrupts can be enabled to
indicate when battery switchover occurs and when the V
power supply is restored (see the Power Supply Management
(PSM) Interrupt section.)
V
The following three events switch the internal power supply
(V
Switching from V
To switch V
must be true:
POWER SUPPLY MANAGEMENT (PSM) INTERRUPT
The power supply management (PSM) interrupt alerts the 8052
core of power supply events. The PSM interrupt is disabled by
default. Setting the EPSM bit in the interrupt enable and Priority 2
SFR (IEIP2, Address 0xA9) enables the PSM interrupt (see
Table 82).
The power management interrupt enable SFR (IPSME,
Address 0xEC) controls the events that result in a PSM interrupt
(see Table 20).
Figure 31 illustrates how the PSM interrupt vector is shared among
the PSM interrupt sources. The PSM interrupt flags are latched
and must be cleared by writing to the IPSMF power management
interrupt flag SFR, Address 0xF8 (see Table 17).
DD
BAT
SWOUT
to V
V
from V
BATPRG[1:0] bits in the battery switchover configuration
SFR (BATPR, Address 0xF5) = 0b01.
V
from V
the BATPR SFR are cleared.
Falling edge on BCTRL. When the battery control pin,
BCTRL, goes low, V
external switchover signal can trigger a switchover to V
at any time. Setting the INT1PRG bits to 0bx01 in the inter-
rupt pins configuration SFR (INTPR, Address 0xFF) enables
the battery control pin (see Table 16).
V
above 2.75 V.
V
is enabled, V
above 1.2 V and V
Rising edge on BCTRL. If the battery control pin is enabled,
V
first or second bullet point is satisfied.
is being used for V
DCIN
DD
DD
DCIN
SWOUT
) from V
BAT
> 2.75 V. V
< 2.75 V. When V
< 1.2 V. When V
> 1.2 V and V
DD
SWOUT
DD
switches back to V
to V
to V
DD
from V
SWOUT
BAT
to V
BAT
BAT
SWOUT
. This event is enabled when BATPRG[1:0] in
. This event is enabled when the
to V
DD
switches to V
BAT
SWOUT
DD
SWOUT
BAT
switches back to V
remains above 2.75 V.
:
DCIN
DD
DD
> 2.75 V. If the low V
to V
.
falls below 2.75 V, V
falls below 1.2 V, V
switches from V
DD
DD
after BCTRL is high, and the
ADE5166/ADE5169
, all of the following events
DD
after V
DD
DD
after V
to V
DCIN
DD
SWOUT
DCIN
to V
SWOUT
BAT
remains
DD
condition
and back.
switches
BAT
remains
switches
. This
DD
BAT

Related parts for ADE5166_08