ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 118

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE5166/ADE5169
Table 137. Leap Years—Rollover After 29 Days
Year Register
0d04
0d08
0d12
0d16
0d20
0d24
0d28
0d32
0d36
0d40
0d44
0d48
0d52
0d56
0d60
0d64
0d68
0d72
0d76
0d80
0d84
0d88
0d92
0d96
RTC INTERRUPTS
The RTC alarm and interval timer interrupts are enabled by
setting the ETI bit in the interrupt enable and Priority 2 SFR
(IEIP2, Address 0xA9). When an alarm or interval timer event
occurs, the corresponding flag is set and a pending RTC interrupt
is generated. If the RTC interrupt is enabled, the program vectors
to the RTC interrupt address, and the corresponding RTC flag
can be cleared in software. Moving to the RTC interrupt address
alone does not automatically clear the flag. To successfully
acknowledge the interrupt event, the flag has to be cleared by
software. If the RTC interrupt is disabled when the event occurs,
the pending interrupt remains until the corresponding RTC flag
is cleared. The ALFLAG and ITFLAG flags, therefore, drive the
RTC interrupt and should be managed by the user to keep track
of the RTC events.
Note that, if the ADE5166/ADE5169 are awakened by an RTC
event, either the ALFLAG or ITFLAG, then the pending RTC
interrupt must be serviced before the ADE5166/ADE5169 can
go back to sleep again. The ADE5166/ADE5169 keep waking up
until this interrupt has been serviced.
Estimated Year
2004
2008
2012
2016
2020
2024
2028
2032
2036
2040
2044
2048
2052
2056
2060
2064
2068
2072
2076
2080
2084
2088
2092
2096
Rev. 0 | Page 118 of 148
Interval Timer Alarm
The RTC can be used as an interval timer. When the interval timer
is enabled by setting the ITEN bit in the RTC configuration SFR
(TIMECON, Address 0xA1[1]), the interval timer clock source
selected by the ITS1 and ITS0 bits (TIMECON, Bits[5:4]) is passed
through to an 8-bit counter. This counter increments on every
interval timer clock pulse until the 8-bit counter is equal to the
value in the alarm interval register. Then an alarm event is gener-
ated, setting the ITFLAG bit (TIMECON, Address 0xA1[2]) and
creating a pending RTC interrupt. If the SIT bit (TIMECON,
Address 0xA1[3]) is clear, the 8-bit counter is cleared and starts
counting again. If the SIT bit is set, the 8-bit counter is held in
reset after the alarm occurs.
Take care when changing the interval timer timebase. The
recommended procedure is as follows:
1.
2.
3.
4.
Alarm
The RTC can be used with an alarm to wake up periodically. The
alarm registers (AL_SEC, AL_MIN, AL_HOUR, AL_DAY, and
AL_DATE) should be set to the specific time that the alarm event
is required, and the corresponding Alxx_EN bits set in the
TIMECON2 SFR (Address 0xA2). The enabled alarm registers
are then compared to their respective RTC registers (SEC, MIN,
HOUR, DAY, and DATE) and when all enabled alarms match
their corresponding RTC registers, the alarm flag is set and a
pending interrupt is generated. The alarm flag is located in Bit 6
of the TIMECON SFR (Address 0xA1). If enabled, an RTC
interrupt occurs and the program vectors to the RTC interrupt
address.
If the INTVAL register is going to be modified, write to the
INTVAL register first. Then wait for one 128 Hz clock cycle
to synchronize with the RTC, 64,000 cycles at a 4.096 MHz
instruction cycle clock.
Disable the interval timer by clearing the ITEN bit (Bit 1)
in the TIMECON SFR. Then wait for one 128 Hz clock cycle
to synchronize with the RTC, 64,000 cycles at a 4.096 MHz
instruction cycle clock.
Read the TIMECON SFR to ensure that the ITEN bit is
clear. If it is not, wait for another 128 Hz clock cycle.
Set the timebase bits, ITS1 and ITS0 (Bits 5:4) in the
TIMECON SFR to configure the interval. Wait for a 128 Hz
clock cycle for this change to take effect.