ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 125

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

Because Timer 2 has 16-bit autoreload capability, very low baud
rates are still possible. Timer 2 is selected as the baud rate generator
by setting TCLK and/or RCLK in Timer/Counter 2 control SFR
(T2CON, Address 0xC8). The baud rates for transmit and receive
can be simultaneously different. Setting RCLK and/or TCLK puts
Timer 2 into its baud rate generator mode, as shown in Figure 102.
In this case, the baud rate is given by the following formula:
UART Timer Generated Baud Rates
The high integer dividers in a UART block mean that high speed
baud rates are not always possible. In addition, generating baud
rates requires the exclusive use of a timer, rendering it unusable
for other applications when the UART is required. To address
this problem, each ADE5166/ADE5169 has a dedicated baud
rate timer (UART timer) specifically for generating highly
accurate baud rates. The UART timer can be used instead of
Timer 1 or Timer 2 for generating very accurate high speed
UART baud rates, including 115,200 bps. This timer also allows
a much wider range of baud rates to be obtained. In fact, every
desired bit rate from 12 bps to 393,216 bps can be generated to
within an error of ±0.8%. The UART timer also frees up the other
three timers, allowing them to be used for different applications.
A block diagram of the UART timer is shown in Figure 101.
Mode 1 or Mode 3 Baud Rate =
(
16
×
[
65536
(P1.3/T2EX/FP24)
(P1.4/T2/FP23)
−
(
RCAP
T2EX PIN
T2 PIN
TRANSITION
f
DETECTOR
CORE
f
CORE
NOTE: AVAILABILITY OF ADDITIONAL
EXTERNAL INTERRUPT
2
H
:
RCAP
2
L
)
]
C/ T2 = 0
C/ T2 = 1
)
EXEN2
CONTROL
CONTROL
TR2
Figure 102. Timer 2, UART Baud Rates
EXF 2
Rev. 0 | Page 125 of 148
RCAP2L
(8 BITS)
TL2
TIMER 2
INTERRUPT
RCAP2H
(8 BITS)
Two SFRs, enhanced serial baud rate control SFR (SBAUDT,
Address 0x9E) and UART timer fractional divider SFR (SBAUDF,
Address 0x9D), are used to control the UART timer. SBAUDT is
the baud rate control SFR; it sets up the integer divider (DIV) and
the extended divider (SBTH) for the UART timer.
The appropriate value to write to DIV (Bits[2:0]) and SBTH
(Bits[4:3]) can be calculated using the following formula, where
f
the DIV value must be rounded down to the nearest integer.
CORE
TH2
FRACTIONAL
DIVIDER
is defined in the POWCON SFR (see Table 25). Note that
DIV
RELOAD
OVERFLOW
P1.4/T2/FP23
TIMER 2
+
SBTH
÷(1 + SBAUDF/64)
÷2
Figure 101. UART Timer, UART Baud Rate
f
DIV + SBTH
÷32
CORE
=
log
1
1
OVERFLOW
2
UART TIMER
⎛
⎜
⎜
⎝
Rx/Tx CLOCK
16
TIMER 1
0
0
0
×
log
Rx CLOCK
TIMER 1/TIMER 2
Baud
f
1
CORE
( )
2
1
1
RCLK
TCLK
ADE5166/ADE5169
16
16
Rate
Tx CLOCK
0
0
SMOD
TIMER 1/TIMER 2
⎞
⎟
⎟
⎠
Rx
CLOCK
Tx
CLOCK
UARTBAUDEN
Rx CLOCK
Tx CLOCK