ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 75

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

Bit
4
[3:2]
[1:0]
BASIC 8052 REGISTERS
Program Counter (PC)
The program counter holds the 2-byte address of the next instruc-
tion to be fetched. The PC is initialized with 0x00 at reset and is
incremented after each instruction is performed. Note that the
amount that is added to the PC depends on the number of bytes
in the instruction; therefore, the increment can range from one
to three bytes. The program counter is not directly accessible to
the user but can be directly modified by CALL and JMP instruc-
tions that change which part of the program is active.
Instruction Register (IR)
The instruction register holds the opcode of the instruction being
executed. The opcode is the binary code that results from assem-
bling an instruction. This register is not directly accessible to
the user.
Register Banks
There are four banks, each containing an 8-byte-wide register,
for a total of 32 bytes of registers. These registers are convenient
for temporary storage of mathematical operands. An instruction
involving the accumulator and a register can be executed in one
clock cycle, as opposed to two clock cycles to perform an instruc-
tion involving the accumulator and a literal or a byte of general-
purpose RAM. The register banks are located in the first 32 bytes
of RAM.
The active register bank is selected by the RS0 and RS1 bits in
the program status word SFR (PSW, Address 0xD0).
Accumulator
The accumulator is a working register, storing the results of
many arithmetic or logical operations. The accumulator is used
in more than half of the 8052 instructions where it is usually
referred to as A. The status register (PSW) constantly monitors
the number of bits that are set in the accumulator to determine
if it has even or odd parity. The accumulator is stored in the
SFR space (see Table 56).
Mnemonic
MOD38EN
Reserved
XREN1,
XREN0
Default
0
00
01
38 kHz modulation enable bit.
Reserved. These bits should be kept at 0 for proper operation.
Description
MOD38EN
0
1
XREN1, XREN0
XREN1 or XREN0 = 1
XREN1 and XREN0 = 0
Rev. 0 | Page 75 of 148
Result
38 kHz modulation is disabled
38 kHz modulation is enabled on the pins selected by the MOD38 bits in the
EPCFG SFR (Address 0x9F[7:0])
Result
Enable MOVX instruction to use 256 bytes of extended RAM
Disable MOVX instruction
B Register
The B register is used by the multiply and divide instructions,
MUL AB and DIV AB, to hold one of the operands. Because it
is not used for many instructions, it can be used as a scratch pad
register like those in the register banks. The B register is stored
in the SFR space (see Table 56).
Program Status Word (PSW)
The PSW register (PSW, Address 0xD0) reflects the status of
arithmetic and logical operations through carry, auxiliary carry,
and overflow flags. The parity flag reflects the parity of the contents
of the accumulator, which can be helpful for communication
protocols. The program status word SFR is bit addressable (see
Table 57).
Data Pointer (DPTR)
The data pointer SFR (DPTR, Address 0x82 and Address 0x83)
is made up of two 8-bit registers: DPL (low byte, Address 0x82),
and DPH (high byte, Address 0x83). These SFRs provide memory
addresses for internal code and data access. The DPTR can be
manipulated as a 16-bit register (DPTR = DPH, DPL) or as two
independent 8-bit registers (DPH and DPL) (see Table 59 and
Table 60).
The 8052 MCU core architecture supports dual data pointers
(see the 8052 MCU Core Architecture section).
Stack Pointer (SP)
The stack pointer SFR (SP, Address 0x81) keeps track of the
current address of the top of the stack. To push a byte of data
onto the stack, the stack pointer is incremented and the data is
moved to the new top of the stack. To pop a byte of data off the
stack, the top byte of data is moved into the awaiting address
and the stack pointer is decremented. The stack is a last in first
out (LIFO) method of data storage because the most recent
addition to the stack is the first to come off it.
The stack is used during CALL and RET instructions to keep
track of the address to move into the PC when returning from
the function call. The stack is also manipulated when vectoring
for interrupts, to keep track of the prior state of the PC.
ADE5166/ADE5169