ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 95

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

Table 98. LCD Pointer SFR (LCDPTR, Address 0xAC)
Bit
7
6
[5:4]
[3:0]
Table 99. LCD Data SFR (LCDDAT, Address 0xAE)
Bit
[7:0]
Table 100. LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED)
Bit
[7:4]
3
2
1
0
LCD SETUP
The LCD configuration SFR (LCDCON, Address 0x95) configures
the LCD module to drive the type of LCD in the user end system.
The BIAS bit (Bit 2) and the LMUX bits (Bits[1:0]) in this SFR
should be set according to the LCD specifications.
The COM2/FP28 and COM3/FP27 pins default to LCD segment
lines. Selecting the 3× multiplex level in the LCD configuration
SFR (LCDCON, Address 0x95) by setting LMUX[1:0] to 10
changes the FP28 pin functionality to COM2. The 4× multiplex
level selection, LMUX[1:0] = 11, changes the FP28 pin function-
ality to COM2 and the FP27 pin functionality to COM3.
The LCD segments of FP0 to FP15 are enabled by default.
Additional pins are selected for LCD functionality in the LCD
segment enable SFR (LCDSEGE, Address 0x97) and LCD
Segment Enable 2 SFR (LCDSEGE2, Address 0xED) where
there are individual enable bits for the FP16 to FP25 segment
pins. The LCD pins do not have to be enabled sequentially. For
example, if the alternate function of FP23, the Timer 2 input, is
required, any of the other shared pins, FP16 to FP25, can be
enabled instead.
The Display Element Control section contains details about setting
up the LCD data memory to turn individual LCD segments on
and off. Setting the LCDRST bit (Bit 6) in the LCD configuration
SFR (LCDCON, Address 0x95) resets the LCD data memory to
its default (0). A power-on reset also clears the LCD data memory.
Mnemonic
Reserved
FP19EN
FP18EN
FP17EN
FP16EN
Mnemonic
R/W
Reserved
RAM2SCREEN
ADDRESS
Mnemonic
LCDDATA
Default
0
0
0
0
0
Default
0
Default
0
0
0
0
Description
Read or write LCD bit. If this bit is set to 1, the data in the LCD data SFR (LCDDAT, Address 0xAE)
is written to the address indicated by the ADDRESS bits (LCDPTR[3:0]).
Reserved.
These bits select the screen recipient of the data memory action.
LCD memory address (see Table 101).
Description
Reserved.
FP19 function select bit. 0 = general-purpose I/O, 1 = LCD function.
FP18 function select bit. 0 = general-purpose I/O, 1 = LCD function.
FP17 function select bit. 0 = general-purpose I/O, 1 = LCD function.
FP16 function select bit. 0 = general-purpose I/O, 1 = LCD function.
Description
Data to be written into or read out of the LCD memory SFRs.
Rev. 0 | Page 95 of 148
LCD TIMING AND WAVEFORMS
An LCD segment acts like a capacitor that is charged and dis-
charged at a certain rate. This rate, the refresh rate, determines
the visual characteristics of the LCD. A slow refresh rate results
in the LCD blinking on and off between refreshes. A fast refresh
rate presents a screen that appears to be continuously lit. In
addition, a faster refresh rate consumes more power.
The frame rate, or refresh rate, for the LCD module is derived
from the LCD clock, f
or 128 Hz by the CLKSEL bit (Bit 3) in the LCD configuration
SFR (LCDCON, Address 0x95). The minimum refresh rate
needed for the LCD to appear solid (without blinking) is
independent of the multiplex level.
The LCD waveform frequency, f
the LCD switches the active common line. Thus, the LCD
waveform frequency depends heavily on the multiplex level.
The frame rate and LCD waveform frequency are set by f
the multiplex level, and the FD[3:0] frame rate selection bits in
the LCD clock SFR (LCDCLK, Address 0x96).
The LCD module provides 16 different frame rates for f
2048 Hz, ranging from 8 Hz to 128 Hz for an LCD with 4×
multiplexing. Fewer options are available with f
ranging from 8 Hz to 32 Hz for a 4× multiplexed LCD. The
128 Hz clock is beneficial for battery operation because it consumes
less power than the 2048 Hz clock. The frame rate is set by the
FD[3:0] bits in the LCD clock SFR (LCDCLK, Address 0x96);
see Table 95 and Table 96.
The LCD waveform is inverted at twice the LCD waveform fre-
quency, f
ADC offset degrades the lifetime and performance of the LCD.
LCD
. This way, each frame has an average dc offset of 0.
LCDCLK
. The LCD clock is selected as 2048 Hz
LCD
ADE5166/ADE5169
, is the frequency at which
LCDCLK
= 128 Hz,
LCDCLK
LCDCLK
=
,