ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 43

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ANALOG-TO-DIGITAL CONVERSION
Each ADE5166/ADE5169 has two Σ-Δ analog-to digital converters
(ADCs). The outputs of these ADCs are mapped directly to wave-
form sampling SFRs (Address 0xE2 to Address 0xE7) and are used
for energy measurement internal digital signal processing. In PSM1
(battery) mode and PSM2 (sleep) mode, the ADCs are powered
down to minimize power consumption.
For simplicity, the block diagram in Figure 41 shows a first-order
Σ -Δ ADC. The converter is made up of the Σ -Δ modulator and
the digital low-pass filter (LPF).
A Σ -Δ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE5166/ADE5169, the sampling clock is equal to
4.096 MHz/5. The 1-bit DAC in the feedback loop is driven by
the serial data stream. The DAC output is subtracted from the
input signal. If the loop gain is high enough, the average value of
the DAC output (and, therefore, the bit stream) can approach
that of the input signal level.
For any given input value in a single sampling interval, the data
from the 1-bit ADC is virtually meaningless. Only when a large
number of samples are averaged is a meaningful result obtained.
This averaging is carried into the second part of the ADC, the
digital LPF. By averaging a large number of bits from the mod-
ulator, the low-pass filter can produce 24-bit data-words that are
proportional to the input signal level.
The Σ -Δ converter uses two techniques to achieve high resolution
from what is essentially a 1-bit conversion technique. The first
is oversampling. Oversampling means that the signal is sampled
at a rate (frequency) that is many times higher than the bandwidth
of interest. For example, the sampling rate in the ADE5166/
ADE5169 is 4.096 MHz/5 (819.2 kHz), and the band of interest
LOW-PASS FILTER
ANALOG
R
C
+
–
Figure 41. First-Order
INTEGRATOR
Rev. 0 | Page 43 of 148
V
REF
1-BIT DAC
is 40 Hz to 2 kHz. Oversampling has the effect of spreading the
quantization noise (noise due to sampling) over a wider band-
width. With the noise spread more thinly over a wider bandwidth,
the quantization noise in the band of interest is lowered (see
Figure 40).
SIGNAL
SIGNAL
However, oversampling alone is not efficient enough to improve
the signal-to-noise ratio (SNR) in the band of interest. For example,
an oversampling ratio of four is required to increase the SNR by
only 6 dB (1 bit). To keep the oversampling ratio at a reasonable
level, it is possible to shape the quantization noise so that the
majority of the noise lies at the higher frequencies. In the Σ -Δ
modulator, the noise is shaped by the integrator, which has a
high-pass-type response for the quantization noise. The result
is that most of the noise is at the higher frequencies where it can
be removed by the digital LPF. This noise shaping is shown in
Figure 40.
MCLK/5
... 10100101 ...
Σ
-∆ ADC
NOISE
NOISE
COMPARATOR
LATCHED
0
0
Figure 40. Noise Reduction Due to Oversampling and
OUTPUT FROM DIGITAL
2
2
Noise Shaping in the Analog Modulator
HIGH RESOLUTION
DIGITAL
FILTER
LPF
LOW-PASS
DIGITAL
FILTER
FREQUENCY (kHz)
FREQUENCY (kHz)
FILTER (RC)
ANTIALIAS
409.6
409.6
24
ADE5166/ADE5169
SHAPED
NOISE
FREQUENCY
SAMPLING
819.2
819.2