ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 137

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

I
The ADE5166/ADE5169 support a fully licensed I
The I
SDATA (P0.4/MOSI/SDATA) is the data I/O pin, and SCLK
(P0.6/SCLK/T0) is the serial clock. These two pins are shared with
the MOSI and SCLK pins of the on-chip SPI interface. Therefore,
the user can enable only one interface or the other on these pins at
any given time. The SCPS bit (Bit 5) in the configuration SFR
(CFG, Address 0xAF) selects which peripheral is active.
The two pins used for data transfer, SDATA and SCLK, are
configured in a wire-AND format that allows arbitration in a
multimaster system.
The transfer sequence of an I
initiating a transfer by generating a start condition while the bus
is idle. The master transmits the address of the slave device and
the direction of the data transfer in the initial address transfer. If
the slave acknowledges, the data transfer is initiated. This continues
until the master issues a stop condition and the bus becomes idle.
SERIAL CLOCK GENERATION
The I
transfer. The master channel can be configured to operate in
fast mode (256 kHz) or standard mode (32 kHz).
Table 156. I
SFR Address
0x9A
0x9B
0xE8
0xE9
0xEA
Table 157. I
Bit
7
[6:5]
[4:0]
Table 158. I
Bit
[7:1]
0
2
C-COMPATIBLE INTERFACE
2
2
C interface is implemented as a full hardware master.
C master in the system generates the serial clock for a
Bit Address
0xEF
0xEE to 0xED
0xEC to 0xE8
Mnemonic
I2CSLVADR
I2CR_W
2
2
2
C SFR List
C Mode SFR (I2CMOD, Address 0xE8)
C Slave Address SFR (I2CADR, Address 0xE9)
Mnemonic
I2CEN
I2CR
I2CRCT
Mnemonic
SPI2CTx
SPI2CRx
I2CMOD
I2CADR
SPI2CSTAT
Default
0
0
2
C system consists of a master device
Default
0
0
0
Description
Address of the I
Command bit for read or write. When this bit is set to Logic 1, a read command is transmitted on the
I
When this bit is set to Logic 0, a write command is transmitted on the I
in the SPI2CTx SFR.
R/W
W
R
R/W
R/W
R/W
2
C bus. Data from the slave in the SPI2CRx SFR (Address 0x9B) is expected after a command byte.
Length
8
8
8
8
8
Description
I
I2CADR SFR (Address 0xE9) starts a communication.
I
I2CR
00
01
10
11
Configures the length of the I
I2CRCT[4:0] + 1 byte have been read, or if an error occurs.
2
2
2
C enable bit. When this bit is set to Logic 1, the I
C SCLK frequency.
C interface.
2
C slave being addressed. Writing to this register starts the I
Rev. 0 | Page 137 of 148
Default
0
0
0
0
Result
f
f
f
f
CORE
CORE
CORE
CORE
/16 = 256 kHz if f
/32 = 128 kHz if f
/64 = 64 kHz if f
/128= 32 kHz if f
The bit rate is defined in the I2CMOD SFR as follows:
SLAVE ADDRESSES
The I
the slave device ID. The LSB of this register contains a read/write
request. A write to this SFR starts the I
I
The I
•
•
•
•
•
Because the SPI and I
they also share the same SFRs, such as the SPI2CTx and SPI2CRx
SFRs. In addition, the I2CMOD, I2CADR, and SPI2CSTAT SFRs
are shared with the SPIMOD1, SPIMOD2, and SPISTAT SFRs,
respectively.
2
C REGISTERS
2
I2CMOD
SPI2CSTAT
I2CADR
SPI2CTx
SPI2CRx
C received FIFO buffer. The I
2
2
f
C slave address SFR (I2CADR, Address 0xE9) contains
C peripheral interface consists of five SFRs.
SCLK
Description
SPI/I
SPI/I
I
I
I
2
2
2
C mode (see Table 157).
C slave address (see Table 158).
C interrupt status register (see Table 159).
=
CORE
2
2
CORE
16
C transmit buffer (see Table 151).
C receive buffer (see Table 152).
CORE
CORE
×
= 4.096 MHz
= 4.096 MHz
f
= 4.096 MHz
= 4.096 MHz
2
CORE
I
2
CR
2
C serial interfaces share the same pins,
: 1 [
2
] 0
C interface is enabled. A write to the
2
2
2
C bus. Data to slave is expected
C transmission (read or write).
C peripheral stops when
ADE5166/ADE5169
2
C communication.