ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 111

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

PLL
The ADE5166/ADE5169 are intended for use with a 32.768 kHz
watch crystal. A PLL locks onto a multiple of this frequency to
provide a stable 4.096 MHz clock for the system. The core can
operate at this frequency or at binary submultiples of it to allow
power savings when maximum core performance is not required.
The default core clock is the PLL clock divided by 4, or 1.024 MHz.
The ADE energy measurement clock is derived from the PLL
clock and is maintained at 4.096 MHz/5 MHz (or 819.2 kHz)
across all CD settings.
PLL REGISTERS
Table 124. Power Control SFR (POWCON, Address 0xC5)
Bit
7
6
5
4
3
[2:0]
Writing to the Power Control SFR (POWCON, Address 0xC5)
Note that writing data to the POWCON SFR involves writing 0xA7 into the key SFR (KYREG, Address 0xC1), followed by a write to the
POWCON SFR.
Table 125. Key SFR (KYREG, Address 0xC1)
Bit
[7:0]
Mnemonic
Reserved
METER_OFF
Reserved
COREOFF
Reserved
CD
Mnemonic
KYREG
Default
1
0
0
0
010
Default
0
Reserved.
Set this bit to 1 to turn off the modulators and energy metering DSP circuitry to reduce power if
metering functions are not needed in PSM0.
This bit should be kept at 0 for proper operation.
Reserved.
Controls the core clock frequency (f
CD
000
001
010
011
100
101
110
111
Description
Set this bit to 1 to shut down the core if in the PSM1 operating mode.
Description
Write 0xA7 to the KYREG SFR before writing to the POWCON SFR to unlock it.
Write 0xEA to the KYREG SFR before writing to the INTPR, HTHSEC, SEC, MIN, or HOUR timekeeping
registers to unlock them (see the RTC Registers section).
Rev. 0 | Page 111 of 148
Result (f
4.096
2.048
1.024
0.512
0.256
0.128
0.064
0.032
CORE
The PLL is controlled by the CD[2:0] bits in the power control
SFR (POWCON, Address 0xC5). To protect erroneous changes
to the POWCON SFR, a key is required to modify the register.
First, the key SFR (KYREG, Address 0xC1) is written with the
key, 0xA7, and then a new value is written to the POWCON SFR.
If the PLL loses lock, the MCU is reset and the PLL_FLT bit
(Bit 4) is set in the peripheral configuration SFR (PERIPH,
Address 0xF4). Set the PLLACK bit in the start ADC measurement
SFR (ADCGO, Address 0xD8) to acknowledge the PLL fault,
clearing the PLL_FLT bit.
). f
CORE
CORE
= 4.096 MHz/2
in MHz)
CD
.
ADE5166/ADE5169