KMPC880ZP66 FREESCALE [Freescale Semiconductor, Inc], KMPC880ZP66 Datasheet - Page 16

• Manufacturer Part Number: KMPC880ZP66
• Description: Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Bus Signal Timing
Table 9
The timing for the MPC885/880 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum
delays. CLKOUT assumes a 100-pF load maximum delay.
16
Core frequency
Bus frequency
Core frequency
Bus frequency
Num
B1a
B1b
B1c
B1d
B1
B2
B3
B4
B5
provides the timings for the MPC885/880 at 33-, 40-, 66-, and 80-MHz bus operation.
Bus period (CLKOUT), see
EXTCLK to CLKOUT phase skew - If
CLKOUT is an integer multiple of
EXTCLK, then the rising edge of EXTCLK
is aligned with the rising edge of CLKOUT.
For a non-integer multiple of EXTCLK, this
synchronization is lost, and the rising
edges of EXTCLK and CLKOUT have a
continuously varying phase skew.
CLKOUT frequency jitter peak-to-peak
Frequency jitter on EXTCLK
CLKOUT phase jitter peak-to-peak
for OSCLK ≥ 15 MHz
CLKOUT phase jitter peak-to-peak
for OSCLK < 15 MHz
CLKOUT pulse width low
(MIN = 0.4
CLKOUT pulse width high
(MIN = 0.4
CLKOUT rise time
CLKOUT fall time
Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)
Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)
Part Frequency
×
×
B1, MAX = 0.6
B1, MAX = 0.6
Characteristic
Part Frequency
MPC885/MPC880 Hardware Specifications, Rev. 3
Table 7
×
×
Table 9. Bus Operation Timings
B1)
B1)
12.1
12.1
Min
–2
—
—
—
—
—
—
—
33 MHz
Min
40
20
66 MHz
Max
18.2
18.2
4.00
4.00
0.50
+2
—
1
4
5
66.67
33.33
Max
10.0
10.0
Min
–2
—
—
—
—
—
—
–
40 MHz
Max
0.50
15.0
15.0
4.00
4.00
+2
—
1
4
5
Min
Min
40
40
40
20
66 MHz
80 MHz
Min
6.1
6.1
–2
—
—
—
—
—
—
—
66 MHz
66.67
66.67
Max
Max
80
40
Max
0.50
4.00
4.00
9.1
9.1
+2
—
1
4
5
Freescale Semiconductor
Min
5.0
5.0
–2
—
—
—
—
—
—
—
80 MHz
Min
Min
40
40
40
20
133 MHz
80 MHz
Max
0.50
4.00
4.00
7.5
7.5
+2
—
1
4
5
Max
Max
133
80
80
66
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
%