KMPC880ZP66 FREESCALE [Freescale Semiconductor, Inc], KMPC880ZP66 Datasheet - Page 2

• Manufacturer Part Number: KMPC880ZP66
• Description: Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Features
Table 1
2 Features
The MPC885/880 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system
integration unit (SIU), and a communications processor module (CPM).
The following list summarizes the key MPC885/880 features:
2
•
•
•
•
MPC885
MPC880
shows the functionality supported by the members of the MPC885 family.
Embedded MPC8xx core up to 133 MHz
Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode)
— The 133-MHz core frequency supports 2:1 mode only.
— The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes.
Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit
general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch and without conditional execution.
— 8-Kbyte data cache and 8-Kbyte instruction cache (see
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces
— Advanced on-chip emulation debug mode
Provides enhanced ATM functionality found on the MPC862 and MPC866 families and includes the
following:
— Improved operation, administration and maintenance (OAM) support
— OAM performance monitoring (PM) support
— Multiple APC priority levels available to support a range of traffic pace requirements
— Port-to-port switching capability without the need for RAM-based microcode
— Simultaneous MII (100BaseT) and UTOPIA (half- or full -duplex) capability
— Optional statistical cell counters per PHY
Part
– Instruction cache is two-way, set-associative with 256 sets in 2 blocks
– Data cache is two-way, set-associative with 256 sets
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache
– Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and
and 16 protection groups
blocks.
are lockable on a cache block basis.
I Cache D Cache 10BaseT
8 Kbyte
8 Kbyte
Cache
MPC885/MPC880 Hardware Specifications, Rev. 3
8 Kbyte
8 Kbyte
Table 1. MPC885 Family
Up to 3
Up to 2
Ethernet
10/100
2
2
SCC SMC USB
3
2
Table
2
2
1)
1
1
UTOPIA interface
UTOPIA interface
Serial ATM and
Serial ATM and
ATM Support
Freescale Semiconductor
Security
Engine
Yes
No