KMPC880ZP66 FREESCALE [Freescale Semiconductor, Inc], KMPC880ZP66 Datasheet - Page 74

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KMPC880ZP66

Manufacturer Part Number
KMPC880ZP66
Description
Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
FEC Electrical Characteristics
Figure 74
15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
Table 37
with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.
Figure 75
74
MII_MDIO (input)
MII_MDC (output)
MII_MDIO (output)
Num
M10
M11
M12
M13
M14
M15
provides information on the MII serial management channel signal timing. The FEC functions correctly
shows the MII asynchronous inputs signal timing diagram.
shows the MII serial management channel timing diagram.
MII_CRS, MII_COL
MII_MDC falling edge to MII_MDIO output invalid (minimum
propagation delay)
MII_MDC falling edge to MII_MDIO output valid (max prop delay)
MII_MDIO (input) to MII_MDC rising edge setup
MII_MDIO (input) to MII_MDC rising edge hold
MII_MDC pulse width high
MII_MDC pulse width low
Figure 75. MII Serial Management Channel Timing Diagram
Table 37. MII Serial Management Channel Timing
MPC885/MPC880 Hardware Specifications, Rev. 3
Figure 74. MII Async Inputs Timing Diagram
M12
Characteristic
M13
M14
M9
M10
M11
MM15
40%
40%
Min
10
0
0
Max
60%
60%
25
Freescale Semiconductor
MII_MDC period
MII_MDC period
Unit
ns
ns
ns
ns

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