KMPC880ZP66 FREESCALE [Freescale Semiconductor, Inc], KMPC880ZP66 Datasheet - Page 62

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KMPC880ZP66

Manufacturer Part Number
KMPC880ZP66
Description
Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
CPM Electrical Characteristics
62
1
2
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2/1.
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
Num
134
138
139
RENA(CD1)
CLSN(CTS1)
TENA inactive delay (from TCLK1 rising edge)
CLKO1 low to SDACK asserted
CLKO1 low to SDACK negated
RCLK1
(Input)
(Input)
RxD1
(Input)
Figure 61. Ethernet Collision Timing Diagram
Figure 62. Ethernet Receive Timing Diagram
MPC885/MPC880 Hardware Specifications, Rev. 3
Table 24. Ethernet Timing (continued)
Characteristic
2
2
121
124
120
125
121
126
123
All Frequencies
Min
Last Bit
10
127
Freescale Semiconductor
Max
50
20
20
Unit
ns
ns
ns

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