KMPC880ZP66 FREESCALE [Freescale Semiconductor, Inc], KMPC880ZP66 Datasheet - Page 53
KMPC880ZP66
Manufacturer Part Number
KMPC880ZP66
Description
Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.KMPC880ZP66.pdf
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CPM Electrical Characteristics
53
1
2
3
4
These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever comes later.
The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
These specs are valid for IDL mode only.
Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.
Num
78A
80A
83a
75
76
77
78
79
80
81
82
83
84
85
86
87
88
L1RSYNC, L1TSYNC rise/fall time
L1RXD valid to L1CLK edge (L1RXD setup time)
L1CLK edge to L1RXD invalid (L1RXD hold time)
L1CLK edge to L1ST(1–4) valid
L1SYNC valid to L1ST(1–4) valid
L1CLK edge to L1ST(1–4) invalid
L1CLK edge to L1TXD valid
L1TSYNC valid to L1TXD valid
L1CLK edge to L1TXD high impedance
L1RCLK, L1TCLK frequency (DSC =1)
L1RCLK, L1TCLK width low (DSC =1)
L1RCLK, L1TCLK width high (DSC = 1)
L1CLK edge to L1CLKO valid (DSC = 1)
L1RQ valid before falling edge of L1TSYNC
L1GR setup time
L1GR hold time
L1CLK edge to L1SYNC valid (FSD = 00) CNT = 0000, BYT = 0,
DSC = 0)
2
MPC885/MPC880 Hardware Specifications, Rev. 3
Characteristic
Table 21. SI Timing (continued)
4
4
3
4
P + 10
P + 10
17.00
13.00
10.00
10.00
10.00
10.00
10.00
42.00
42.00
0.00
1.00
All Frequencies
Min
—
—
—
—
SYNCCLK
16.00 or
15.00
45.00
45.00
45.00
55.00
55.00
42.00
30.00
Max
0.00
Freescale Semiconductor
—
—
—
—
—
—
—
/2
L1TCLK
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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