KMPC880ZP66 FREESCALE [Freescale Semiconductor, Inc], KMPC880ZP66 Datasheet - Page 34

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KMPC880ZP66

Manufacturer Part Number
KMPC880ZP66
Description
Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Bus Signal Timing
Figure 20
Figure 21
34
provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM.
GPL_A[0:5],
provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM.
GPL_A[0:5],
GPL_B[0:5]
GPL_B[0:5]
Figure 20. Asynchronous UPWAIT Asserted Detection in UPM-Handled Cycles Timing
BS_A[0:3],
BS_A[0:3],
Figure 21. Asynchronous UPWAIT Negated Detection in UPM-Handled Cycles Timing
BS_B[0:3]
BS_B[0:3]
CLKOUT
CLKOUT
UPWAIT
UPWAIT
CSx
CSx
B37
B37
MPC885/MPC880 Hardware Specifications, Rev. 3
B38
B38
Freescale Semiconductor

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