KMPC880ZP66 FREESCALE [Freescale Semiconductor, Inc], KMPC880ZP66 Datasheet - Page 35

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KMPC880ZP66

Manufacturer Part Number
KMPC880ZP66
Description
Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Bus Signal Timing
Figure 22
Figure 23
Figure 24
35
Figure 23. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)
CSx, WE[0:3],
R/W, BURST
provides the timing for the synchronous external master access controlled by the GPCM.
provides the timing for the asynchronous external master memory access controlled by the GPCM.
provides the timing for the asynchronous external master control signals negation.
TSIZ[0:1],
CLKOUT
Figure 22. Synchronous External Master Access Timing (GPCM Handled—ACS = 00)
OE, GPLx,
TSIZ[0:1],
A[0:31],
CLKOUT
A[0:31],
BS[0:3]
R/W
CSx
AS
Figure 24. Asynchronous External Master—Control Signals Negation Timing
CSx
TS
AS
MPC885/MPC880 Hardware Specifications, Rev. 3
B40
B39
B41
B40
B42
B43
B22
B22
Freescale Semiconductor

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