PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 119

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

Register 14-2: SSPCON1: MSSP Control Register1
bit 7
bit 6
bit 5
bit 4
bit 3 - 0
7/99 Microchip Technology Inc.
bit 7
WCOL: Write Collision Detect bit
Master Mode:
1 = A write to the SSPBUF register was attempted while the I
0 = No collision
Slave Mode:
1 = The SSPBUF register is written while it is still transmitting the previous word must be cleared in software)
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow,
0 = No overflow
In I
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care"
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output.
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
In I
Unused in this mode
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI master mode, clock = F
0001 = SPI master mode, clock = F
0010 = SPI master mode, clock = F
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
0110 = I
0111 = I
1000 = I
1001 = Reserved
1010 = Reserved
1011 = I
1100 = Reserved
1101 = Reserved
1110 = I
1111 = I
Legend:
R = Readable bit
- n = Value at POR reset
WCOL
R/W-0
SSPBUF, even if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not
set since each new reception (and transmission) is initiated by writing to the SSPBUF register. (Must be
cleared in software)
2
2
2
2
to be started
the data in SSPSR is lost. Overflow can only occur in slave mode. In slave mode the user must read the
in transmit mode. (Must be cleared in software)
C mode:
C mode:
C slave mode:
C master mode
2
2
2
2
2
2
C slave mode, 7-bit address
C slave mode, 10-bit address
C master mode, clock = F
C firmware controlled Master mode (Slave idle)
C slave mode, 7-bit address with start and stop bit interrupts enabled
C slave mode, 10-bit address with start and stop bit interrupts enabled
SSPOV
R/W-0
SSPEN
R/W-0
W = Writable bit
’1’ = Bit is set
OSC
OSC
OSC
OSC
/4
/16
/64
/ (4 * (SSPADD+1) )
R/W-0
CKP
Preliminary
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
2
SSPM3
R/W-0
C conditions were not valid for a transmission
SSPM2
R/W-0
x = Bit is unknown
SSPM1
R/W-0
PIC18CXX2
bit 0
SSPM0
R/W-0
DS39026B-page 119