PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 24

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18CXX2
3.1
A Power-on Reset pulse is generated on-chip when
V
cuitry, just tie the MCLR pin directly (or through a resis-
tor) to V
usually needed to create a Power-on Reset delay. A
maximum rise time for V
D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature,...) must be met to ensure oper-
ation. If these conditions are not met, the device must
be held in reset until the operating conditions are met.
Brown-out Reset may be used to meet the voltage
start-up condition.
FIGURE 3-2:
DS39026B-page 24
Note 1: External Power-on Reset circuit is required
DD
rise is detected. To take advantage of the POR cir-
2: R < 40 k is recommended to make sure
3: R1 = 100 to 1 k will limit any current
DD
Power-On Reset (POR)
. This will eliminate external RC components
only if the V
The diode D helps discharge the capacitor
quickly when V
that the voltage drop across R does not
violate the device’s electrical specification.
flowing into MCLR from external capacitor
C in the event of MCLR/V
down due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
D
V
DD
EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
V
R
DD
C
DD
POWER-UP)
power-up slope is too slow.
DD
DD
R1
powers down.
is specified (parameter
PIC18CXXX
MCLR
PP
pin break-
Preliminary
3.2
The Power-up Timer provides a fixed nominal time-out
(parameter #33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in reset as long as the PWRT is active.
The PWRT’s time delay allows V
able level. A configuration bit is provided to enable/dis-
able the PWRT.
The power-up time delay will vary from chip-to-chip due
to V
parameter #33 for details.
3.3
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and stabi-
lized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
3.4
With the PLL enabled, the timeout sequence following
a power-on reset is different from other oscillator
modes. A portion of the Power-up Timer is used to pro-
vide a fixed timeout that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock timeout
(T
timeout (OST).
3.5
A configuration bit, BOREN, can disable (if clear/pro-
grammed) or enable (if set) the Brown-out Reset cir-
cuitry. If V
than parameter #35, the brown-out situation will reset
the chip. A reset may not occur if V
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until V
BV
keep the chip in RESET an additional time delay
(parameter #33). If V
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be initial-
ized. Once V
will execute the additional time delay.
PLL
DD
DD
) is typically 2 ms and follows the oscillator startup
. The Power-up Timer will then be invoked and will
, temperature and process variation. See DC
Power-up Timer (PWRT)
Oscillator Start-up Timer (OST)
PLL Lock Timeout
Brown-Out Reset (BOR)
DD
DD
falls below parameter D005 for greater
rises above BV
DD
drops below BV
7/99 Microchip Technology Inc.
DD
DD
, the Power-up Timer
to rise to an accept-
DD
DD
DD
rises above
falls below
while the