PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 161

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

15.3
In Synchronous Master mode, the data is transmitted in
a half-duplex manner, (i.e. transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
15.3.1
The USART transmitter block diagram is shown in
Figure 15-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and inter-
rupt bit TXIF (PIR1<4>) is set. The interrupt can be
TABLE 15-8:
Name
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
SPBRG Baud Rate Generator Register
Legend: x = unknown, — = unimplemented, read as '0'.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
7/99 Microchip Technology Inc.
USART Synchronous Master Mode
USART SYNCHRONOUS MASTER
TRANSMISSION
Shaded cells are not used for Synchronous Master Transmission.
PSPIF
PSPIE
PSPIP
USART Transmit Register
CSRC
SPEN
GIEH
Bit 7
GIE/
(1)
(1)
(1)
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
PEIE/
ADIE
ADIP
GIEL
ADIF
Bit 6
RX9
TX9
TMR0IE INT0IE
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
CREN
SYNC
Bit 4
TXIF
TXIE
TXIP
SSPIF CCP1IF
SSPIE CCP1IE TMR2IE
SSPIP CCP1IP TMR2IP
RBIE
Bit 3
Preliminary
—
—
TMR0IF
BRGH
FERR
Bit 2
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE, and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit, which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
available to the user.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
2.
3.
4.
5.
6.
7.
Initialize the SPBRG register for the appropriate
baud rate (Section 15.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREG register.
TMR2IF
INT0IF
OERR
TRMT
Bit 1
TMR1IF
TMR1IE
TMR1IP
RX9D
TX9D
RBIF
Bit 0
PIC18CXX2
0000 000x
0000 0000
0000 0000
0000 0000
0000 -00x
0000 0000
0000 -010
0000 0000
Value on
POR,
BOR
DS39026B-page 161
other Resets
Value on all
0000 000u
0000 0000
0000 0000
0000 0000
0000 -00x
0000 0000
0000 -010
0000 0000