PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 120

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18CXX2
Register 14-3: SSPCON2: MSSP Control Register2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39026B-page 120
bit 7
GCEN: General Call Enable bit (In I
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (In I
In master transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (In I
In master receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of
a receive.
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit (In I
In master receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
0 = Acknowledge sequence idle
RCEN: Receive Enable bit (In I
1 = Enables Receive mode for I
0 = Receive idle
PEN: Stop Condition Enable bit (In I
SCK release control
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition idle
RSEN: Repeated Start Condition Enabled bit (In I
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition idle.
SEN: Start Condition Enabled bit (In I
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition idle
Legend:
R = Readable bit
- n = Value at POR reset
Note:
GCEN
R/W-0
Automatically cleared by hardware.
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes
to the SSPBUF are disabled).
ACKSTAT
R/W-0
ACKDT
R/W-0
W = Writable bit
’1’ = Bit is set
2
2
C
C master mode only)
2
2
2
C master mode only)
C master mode only)
C slave mode only)
2
C master mode only)
ACKEN
R/W-0
2
Preliminary
C master mode only)
2
2
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
C master mode only)
C master mode only)
R/W-0
RCEN
2
C module is not in the idle mode,
R/W-0
PEN
x = Bit is unknown
R/W-0
RSEN
7/99 Microchip Technology Inc.
bit 0
R/W-0
SEN