PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 134

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18CXX2
14.3.3
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a reset or when the MSSP module is dis-
abled. Control of the I
bit is set or the bus is idle with both the S and P bits
clear.
In master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge Transmit
• Repeated Start
FIGURE 14-13: MSSP BLOCK DIAGRAM (I
DS39026B-page 134
SDA
SCL
MASTER MODE
2
C bus may be taken when the P
SDA in
Bus Collision
SCL in
Read
MSb
Write collision detect
end of XMIT/RCV
Start bit, Stop bit,
Clock Arbitration
State counter for
Start bit detect
Stop bit detect
Acknowledge
2
Generate
SSPBUF
SSPSR
C MASTER MODE)
Preliminary
LSb
Write
14.3.4
Master Mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. Once master mode is enabled, the user has
six options.
1.
2.
3.
4.
5.
6.
Clock
Data Bus
Shift
Note:
Internal
Assert a start condition on SDA and SCL.
Assert a Repeated Start condition on SDA and
SCL.
Write to the SSPBUF register initiating transmis-
sion of data/address.
Generate a stop Condition on SDA and SCL.
Configure the I
Generate an acknowledge condition at the end
of a received byte of data.
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
I
2
C MASTER MODE SUPPORT
The MSSP Module, when configured in I
Master Mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a start condition and
immediately write the SSPBUF register to
imitate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
2
C port to receive data.
7/99 Microchip Technology Inc.
SSPADD<6:0>
SSPM3:SSPM0
Baud
Rate
Generator
2
C