PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 152

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18CXX2
Register 15-2: RCSTA: Receive Status and Control Register
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39026B-page 152
bit 7
SPEN: Serial Port Enable bit
1 = Serial port enabled (Configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1 = Enables single receive
0 = Disables single receive
Synchronous mode - slave
Unused in this mode
CREN: Continuous Receive Enable bit
Asynchronous mode
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1)
1 = Enables address detection, enable interrupt and load of the receive buffer
0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit
FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
RX9D: 9th bit of received data, can be Address/Data bit or a parity bit.
Legend:
R = Readable bit
- n = Value at POR reset
R/W-0
SPEN
This bit is cleared after reception is complete.
when RSR<8> is set
R/W-0
RX9
R/W-0
SREN
W = Writable bit
’1’ = Bit is set
R/W-0
CREN
Preliminary
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
ADDEN
R/W-0
FERR
R-0
x = Bit is unknown
OERR
R-0
7/99 Microchip Technology Inc.
bit 0
RX9D
R-x