MC68HC705C4ACB MOTOROLA [Motorola, Inc], MC68HC705C4ACB Datasheet - Page 113

• Manufacturer Part Number: MC68HC705C4ACB
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

9.5.2 Mask Option Register 1
MC68HC705C4A • MC68HSC705C4A — Rev. 3.0
MOTOROLA
NOTE:
Address:
IRQ — Interrupt Request Pin Sensitivity Bit
Bits 7–4 and 0 — Not used; always read 0
Bit 2 — Unaffected by reset; reads either 1 or 0
The mask option register 1 (MOR1) shown in
register that enables the port B pullup devices. Data from MOR1 is
latched on the rising edge of the voltage on the RESET pin. (See
Port B
PBPU7–PBPU0/COPC — Port B Pullup Enable Bits 7–0
PBPU0/COPC programmed to a 1 enables the port B pullup bit. This bit
is also used to clear the COP. Writing to this bit to clear the COP will not
affect the state of the port B pullup (bit 0). (See
Operating Properly (COP) Watchdog
Erased:
Reset:
Read:
Write:
IRQ is set only by reset, but can be cleared by software. This bit can
only be written once.
These EPROM bits enable the port B pullup devices.
1 = IRQ pin is both negative edge- and level-sensitive.
0 = IRQ pin is negative edge-sensitive only.
1 = Port B pullups enabled
0 = Port B pullups disabled
Interrupts.)
PBPU7
$1FF0
Bit 7
0
Figure 9-5. Mask Option Register 1 (MOR1)
EPROM/OTPROM (PROM)
PBPU6
6
0
PBPU5
5
0
Unaffected by reset
PBPU4
4
0
Reset.)
PBPU3
3
0
Figure 9-5
5.3.3 Computer
EPROM/OTPROM (PROM)
PBPU2
2
0
PBPU1
Control Registers
is an EPROM
1
0
Technical Data
PBPU0/
COPC
4.3.3
Bit 0
0
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