MC68HC705C4ACB MOTOROLA [Motorola, Inc], MC68HC705C4ACB Datasheet - Page 55

• Manufacturer Part Number: MC68HC705C4ACB
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

4.3.3 Port B Interrupts
MC68HC705C4A • MC68HSC705C4A — Rev. 3.0
MOTOROLA
NOTE:
The IRQ pin is negative edge-triggered only or negative edge- and low
level-triggered, depending on the external interrupt triggering mask
option selected.
When the edge- and level-triggering mask option is selected:
When the edge-triggering mask option is selected:
If the IRQ pin is not in use, connect it to the V
When these three conditions are true, a port B pin (PBx) acts as an
external interrupt pin:
MOR1 is an erasable, programmable read-only memory (EPROM)
register that enables the port B pullup device. (See
Register
on the RESET pin.
1. The corresponding port B pullup bit (PBPUx) in mask option
2. The corresponding port B data direction bit (DDRBx) in data
3. The clear interrupt mask (CLI) instruction has cleared the I bit in
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A falling edge or a low level on the IRQ pin latches an external
interrupt request.
As long as the IRQ pin is low, an external interrupt request is
present, and the CPU continues to execute the interrupt service
routine. The edge- and level-sensitive trigger option allows
connection to the IRQ pin of multiple wired-OR interrupt sources.
A falling edge on the IRQ pin latches an external interrupt request.
A subsequent external interrupt request can be latched only after
the voltage level on the IRQ pin returns to logic 1 and then falls
again to logic 0.
register 1 (MOR1) is programmed to a logic 1.
direction register B is a logic 0.
the condition code register.
1.) Data from MOR1 is latched on the rising edge of the voltage
Interrupts
DD
pin.
9.5.2 Mask Option
Interrupt Sources
Technical Data
Interrupts
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