MC68HC705C4ACB MOTOROLA [Motorola, Inc], MC68HC705C4ACB Datasheet - Page 48

• Manufacturer Part Number: MC68HC705C4ACB
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Central Processor Unit (CPU)
3.3.5 Condition Code Register
Technical Data
48
The condition code register (CCR) shown in
register whose three most significant bits are permanently fixed at 111.
The condition code register contains the interrupt mask and four bits that
indicate the results of prior instructions. Functions of the condition code
register are described here.
Reset:
H — Half-Carry Bit (H)
I — Interrupt Mask
Read:
Write:
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an add without carry (ADD) or add
with carry (ADC) operation. The half-carry bit is required for
binary-coded decimal (BCD) arithmetic operations. Reset has no
affect on the half-carry flag.
Setting the interrupt mask (I) disables interrupts. If an interrupt
request occurs while the interrupt mask is a logic 0, the CPU saves
the CPU registers on the stack, sets the interrupt mask, and then
fetches the interrupt vector. If an interrupt request occurs while the
interrupt mask is set, the interrupt request is latched. The CPU
processes the latched interrupt as soon as the interrupt mask is
cleared again.
A return from interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After a
reset, the interrupt mask is set and can be cleared only by a clear
interrupt mask bit (CLI), STOP, or WAIT instruction.
Bit 7
1
1
Central Processor Unit (CPU)
Figure 3-6. Condition Code Register (CCR)
= Unimplemented
6
1
1
5
1
1
MC68HC705C4A • MC68HSC705C4A — Rev. 3.0
U
H
4
U = Unaffected
3
1
I
Figure 3-6
U
2
N
is an 8-bit
U
1
Z
MOTOROLA
Bit 0
C
U