SSTUM32868ET/G NXP [NXP Semiconductors], SSTUM32868ET/G Datasheet
SSTUM32868ET/G
Related parts for SSTUM32868ET/G
SSTUM32868ET/G Summary of contents
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SSTUM32868 1.8 V 28-bit configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 02 — 2 March 2007 1. General description The SSTUM32868 is a 1.8 V 28-bit register specifically designed for use ...
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... SSTUM32868ET/G Pb-free (SnAgCu solder ball compound) SSTUM32868ET/S Pb-free (SnAgCu solder ball compound) 4.1 Ordering options Table 2. Type number SSTUM32868ET/G SSTUM32868ET/S SSTUM32868_2 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity 15 mm, 0.65 mm ball pitch TFBGA package Package Name Description TFBGA176 plastic thin fine-pitch ball grid array package; ...
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NXP Semiconductors 5. Functional diagram RESET VREF DCKE0, DCKE1 DODT0, DODT1 DCS0 CSGEN DCS1 DCS2 DCS3 (1) Register A configuration ( D5, D7 D12, D17 to D28 Fig 1. Logic diagram of SSTUM32868 (positive ...
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NXP Semiconductors RESET CK CK (1) Dn VREF PAR_IN DCS0 CSGEN DCS1 DCS2 DCS3 (1) Register A configuration ( D5, D7 D12, D17 to D28 (2) Register A configuration (C = 0): Q1A to ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration for TFBGA176 SSTUM32868_2 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity SSTUM32868ET/G SSTUM32868ET/S ball A1 index area ...
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NXP Semiconductors Fig 4. Ball mapping ( Register SSTUM32868_2 Product data sheet ...
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NXP Semiconductors Fig 5. Ball mapping ( Register SSTUM32868_2 Product data sheet ...
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NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin Register Ungated inputs DCKE0 D1 DCKE1 C1 DODT0 N1 DODT1 P1 Chip Select gated inputs D1 to A2, A1, B2, B1, C2, ...
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NXP Semiconductors Table 3. Pin description …continued Symbol Pin Register QCKE0A F2 QCKE0B H8 QCKE1A E2 QCKE1B F8 QODT0A N2 QODT0B M7 QODT1A P2 QODT1B M8 Output error QERR M3 Parity input PAR_IN ...
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NXP Semiconductors Table 3. Pin description …continued Symbol Pin Register VREF A5, AB5 V B3, B4, B5, B6, D3, D4, DD D5, D6, F3, F4, F5, F6, H3, H4, H5, H6, K4, K5, ...
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NXP Semiconductors Table 4. Function table (each flip-flop) [2] [2] RESET DCS0 DCS1 floating floating [ the previous state of the associated output. 0 [2] DCS2 and ...
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NXP Semiconductors The device supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset ...
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NXP Semiconductors LOW, the QERR output will function normally. The RESET input has priority over the DCSn control, and when driven LOW will force the Qn outputs LOW and the QERR output HIGH. If the chip-select control functionality is not ...
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NXP Semiconductors 7.3 Register timing RESET CSGEN DCSn CK CK Dn, DODTn, (1) DCKEn Qn, QODTn, QCKEn (1) PAR_IN (2) QERR HIGH, LOW, or Don't care (1) After RESET is switched from LOW to HIGH, all data and PAR_IN input ...
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NXP Semiconductors RESET CSGEN DCSn CK CK Dn, DODTn, DCKEn Qn, QODTn, QCKEn PAR_IN (1) QERR unknown input event (1) If the data is clocked in on the m clock pulse, and PAR_IN is clocked ...
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NXP Semiconductors RESET (1) CSGEN (1) DCSn (1) CK (1) CK Dn, DODTn, (1) DCKEn Qn, QODTn, QCKEn (1) PAR_IN QERR (1) After RESET is switched from HIGH to LOW, all data and clock input signals must be held at ...
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... Human Body Model (HBM); 1 100 pF Machine Model (MM 200 pF Conditions [1] Dn, CSR and PAR_IN inputs [1] Dn, CSR and PAR_IN inputs [1] [1] Dn, CSR and PAR_IN inputs [2] RESET, CSGEN [2] RESET, CSGEN CK, CK CK, CK operating in free air SSTUM32868ET/G SSTUM32868ET/S Rev. 02 — 2 March 2007 SSTUM32868 Min Max 0.5 +2.5 [1][2] 0.5 +2.5 [1][ ...
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NXP Semiconductors 10. Characteristics Table 8. Characteristics Over recommended operating conditions, unless otherwise noted. Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input current I I supply current DD I dynamic operating current DDD per ...
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NXP Semiconductors Table 9. Timing requirements Over recommended operating conditions, unless otherwise noted. Symbol Parameter f clock frequency clk t pulse duration W t differential inputs active time ACT t differential inputs inactive INACT time t set-up time su t ...
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NXP Semiconductors 11. Test information 11.1 Parameter measurement information for data output load circuit All input pulses are supplied by generators having the following characteristics: Pulse Repetition Rate (PRR) unless otherwise specified. The outputs are ...
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NXP Semiconductors Fig 12. Voltage waveforms; set-up and hold times Fig 13. Voltage waveforms; propagation delay times (clock to output) Fig 14. Voltage waveforms; propagation delay times (reset to output) SSTUM32868_2 Product data sheet 1.8 V DDR2-800 configurable registered buffer ...
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NXP Semiconductors 11.2 Data output slew rate measurement All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 15. Load circuit, HIGH-to-LOW slew measurement Fig 16. Voltage ...
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NXP Semiconductors 11.3 Error output load circuit and voltage measurement All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 19. Load circuit, error output measurements Fig ...
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NXP Semiconductors Fig 22. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to SSTUM32868_2 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity timing V ICR inputs t PLH output waveform 2 clock inputs Rev. 02 — ...
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NXP Semiconductors 12. Package outline TFBGA176: plastic thin fine-pitch ball grid array package; 176 balls; body 0.7 mm ball A1 index area ...
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NXP Semiconductors 13. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering ...
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NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...
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NXP Semiconductors Fig 24. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 14. Acronym CMOS DDR2 DIMM DRAM LVCMOS PRR RDIMM ...
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NXP Semiconductors 16. Legal information 16.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...