SSTUM32868ET/G NXP [NXP Semiconductors], SSTUM32868ET/G Datasheet - Page 13

• Manufacturer Part Number: SSTUM32868ET/G
• Description: 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SSTUM32868_2
Product data sheet
LOW, the QERR output will function normally. The RESET input has priority over the
DCSn control, and when driven LOW will force the Qn outputs LOW and the QERR output
HIGH. If the chip-select control functionality is not desired, then the CSGEN input can be
hard-wired to ground (GND), in which case the set-up time requirement for DCSn would
be the same as for the other D data inputs. To control the Low-power mode with DCSn
only, the CSGEN input should be pulled up to V
The two VREF pins (A5 and AB5) are connected together internally by approximately
150 . However, it is necessary to connect only one of the two VREF pins to the external
V
capacitor.
The SSTUM32868 is available in a TFGBA176 package.
ref
power supply. An unused VREF pin should be terminated with a V
Rev. 02 — 2 March 2007
1.8 V DDR2-800 configurable registered buffer with parity
DD
through a pull-up resistor.
SSTUM32868
ref
© NXP B.V. 2007. All rights reserved.
coupling
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